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From: Alexandru Stefan ISAILA <aisaila@bitdefender.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>,
	Xen-devel <xen-devel@lists.xenproject.org>
Cc: "Petre Ovidiu PIRCALABU" <ppircalabu@bitdefender.com>,
	"Juergen Gross" <jgross@suse.com>,
	"Tamas K Lengyel" <tamas@tklengyel.com>, "Wei Liu" <wl@xen.org>,
	"Razvan COJOCARU" <rcojocaru@bitdefender.com>,
	"Jan Beulich" <JBeulich@suse.com>,
	"Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [Xen-devel] [PATCH v2 2/3] x86/svm: Always intercept ICEBP
Date: Tue, 26 Nov 2019 12:28:33 +0000	[thread overview]
Message-ID: <f25fdcaf-4b81-898e-3a02-45c57c00e3dc@bitdefender.com> (raw)
In-Reply-To: <20191126120357.13398-3-andrew.cooper3@citrix.com>



On 26.11.2019 14:03, Andrew Cooper wrote:
> ICEBP isn't handled well by SVM.
> 
> The VMexit state for a #DB-vectored TASK_SWITCH has %rip pointing to the
> appropriate instruction boundary (fault or trap, as appropriate), except for
> an ICEBP-induced #DB TASK_SWITCH, where %rip points at the ICEBP instruction
> rather than after it.  As ICEBP isn't distinguished in the vectoring event
> type, the state is ambiguous.
> 
> To add to the confusion, an ICEBP which occurs due to Introspection
> intercepting the instruction, or from x86_emulate() will have %rip updated as
> a consequence of partial emulation required to inject an ICEBP event in the
> first place.
> 
> We could in principle spot the non-injected case in the TASK_SWITCH handler,
> but this still results in complexity if the ICEBP instruction also has an
> Instruction Breakpoint active on it (which genuinely has fault semantics).
> 
> Unconditionally intercept ICEBP.  This does have a trap semantics for the
> intercept, and allows us to move %rip forwards appropriately before the
> TASK_SWITCH intercept is hit.  This makes the behaviour of #DB-vectored
> switches consistent however the ICEBP #DB came about, and avoids special cases
> in the TASK_SWITCH intercept.
> 
> This in turn allows for the removal of the conditional
> hvm_set_icebp_interception() logic used by the monitor subsystem, as ICEBP's
> will now always be submitted for monitoring checks.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

LGTM.

Reviewed-by: Alexandru Isaila <aisaila@bitdefender.com>
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  reply	other threads:[~2019-11-26 12:28 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-26 12:03 [Xen-devel] [PATCH for-4.13 v2 0/3] x86/hvm: Multiple corrections to task switch handling Andrew Cooper
2019-11-26 12:03 ` [Xen-devel] [PATCH v2 1/3] x86/vtx: Fix fault semantics for early task switch failures Andrew Cooper
2019-11-26 12:03 ` [Xen-devel] [PATCH v2 2/3] x86/svm: Always intercept ICEBP Andrew Cooper
2019-11-26 12:28   ` Alexandru Stefan ISAILA [this message]
2019-11-26 15:15   ` Petre Ovidiu PIRCALABU
2019-11-26 15:32   ` Jan Beulich
2019-11-26 15:59     ` Andrew Cooper
2019-11-26 16:05       ` Jan Beulich
2019-11-26 16:11         ` Andrew Cooper
2019-11-26 16:14           ` Jan Beulich
2019-11-26 16:16             ` Andrew Cooper
2019-11-26 15:34   ` Roger Pau Monné
2019-11-26 16:09     ` Andrew Cooper
2019-11-27  8:55       ` Roger Pau Monné
2019-11-26 12:03 ` [Xen-devel] [PATCH v2 3/3] x86/svm: Write the correct %eip into the outgoing task Andrew Cooper
2019-11-26 15:45   ` Jan Beulich
2019-11-28 15:54 ` [Xen-devel] [PATCH for-4.13 v2 0/3] x86/hvm: Multiple corrections to task switch handling Jürgen Groß

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