Re: [PATCH] decodetree: Allow custom var width load functions

From: Richard Henderson <richard.henderson@linaro.org>
To: Luis Pires <luis.pires@eldorado.org.br>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org
Subject: Re: [PATCH] decodetree: Allow custom var width load functions
Date: Tue, 13 Apr 2021 18:10:11 -0700	[thread overview]
Message-ID: <f6cda241-4e11-cfa0-02fe-3119b5d0b8b9@linaro.org> (raw)
In-Reply-To: <20210413181615.414685-1-luis.pires@eldorado.org.br>

On 4/13/21 11:16 AM, Luis Pires wrote:
> This is useful in situations where you want decodetree
> to handle variable width instructions but you want to
> provide custom code to load the instructions. Suppressing
> the generation of the load function is necessary to avoid
> compilation errors due to the load function being unused.
> 
> This will be used by the PowerPC decodetree code.
> 
> Signed-off-by: Luis Pires<luis.pires@eldorado.org.br>
> ---
>   scripts/decodetree.py | 18 +++++++++++-------
>   1 file changed, 11 insertions(+), 7 deletions(-)

So, in the previous cases where we have very controlled "variable length", 
we've simply created separate decode files each with fixed length.

E.g. for arm thumb, in thumb_tr_translate_insn:

     insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
     is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
...
     if (is_16bit) {
         disas_thumb_insn(dc, insn);
     } else {
         disas_thumb2_insn(dc, insn);
     }

Similarly, riscv's decode_opc.

I would think that Power would work the same, with 32-bit and 64-bit 
instructions.  I'd like you to talk me through what you want to do here.

r~