Re: [PATCH] serial: pl010: Drop CR register reset on set_termios

From: Jiri Slaby <jirislaby@kernel.org>
To: Lukas Wunner <lukas@wunner.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Russell King <linux@armlinux.org.uk>,
	Lino Sanfilippo <LinoSanfilippo@gmx.de>,
	Philipp Rosenberger <p.rosenberger@kunbus.com>,
	linux-serial@vger.kernel.org
Subject: Re: [PATCH] serial: pl010: Drop CR register reset on set_termios
Date: Fri, 7 Jan 2022 09:30:48 +0100	[thread overview]
Message-ID: <ffe14471-b5da-fe97-a679-f1066ed13bd2@kernel.org> (raw)
In-Reply-To: <fcaff16e5b1abb4cc3da5a2879ac13f278b99ed0.1641128728.git.lukas@wunner.de>

On 02. 01. 22, 18:42, Lukas Wunner wrote:
> pl010_set_termios() briefly resets the CR register to zero.
> 
> Where does this register write come from?
> 
> The PL010 driver's IRQ handler ambauart_int() originally modified the CR
> register without holding the port spinlock.  ambauart_set_termios() also
> modified that register.  To prevent concurrent read-modify-writes by the
> IRQ handler and to prevent transmission while changing baudrate,
> ambauart_set_termios() had to disable interrupts.  That is achieved by
> writing zero to the CR register.
> 
> However in 2004 the PL010 driver was amended to acquire the port
> spinlock in the IRQ handler, obviating the need to disable interrupts in
> ->set_termios():
> https://git.kernel.org/history/history/c/157c0342e591
> 
> That rendered the CR register write obsolete.  Drop it.
> 
> Signed-off-by: Lukas Wunner <lukas@wunner.de>
> Cc: Russell King <rmk+kernel@armlinux.org.uk>
> ---
>   drivers/tty/serial/amba-pl010.c | 3 ---
>   1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/tty/serial/amba-pl010.c b/drivers/tty/serial/amba-pl010.c
> index e744b953ca34..47654073123d 100644
> --- a/drivers/tty/serial/amba-pl010.c
> +++ b/drivers/tty/serial/amba-pl010.c
> @@ -446,14 +446,11 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios,
>   	if ((termios->c_cflag & CREAD) == 0)
>   		uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
>   
> -	/* first, disable everything */
>   	old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
>   
>   	if (UART_ENABLE_MS(port, termios->c_cflag))
>   		old_cr |= UART010_CR_MSIE;
>   
> -	writel(0, uap->port.membase + UART010_CR);
> -

Isn't the write of zero followed by the original CR value needed to 
actually start the chip with the updated baud rate?

What are you trying to fix?

>   	/* Set baud rate */
>   	quot -= 1;
>   	writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);

thanks,
-- 
js
suse labs