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Message-ID: <1524563292.8691.38.camel@infradead.org>
Subject: [MODERATED] Re: L1D-Fault KVM mitigation
From: David Woodhouse <dwmw2@infradead.org>
In-Reply-To: <20180424093537.GC4064@hirez.programming.kicks-ass.net>
References: <20180424090630.wlghmrpasn7v7wbn@suse.de>
	 <20180424093537.GC4064@hirez.programming.kicks-ass.net>
Date: Tue, 24 Apr 2018 10:48:12 +0100
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To: speck@linutronix.de
List-ID: <speck.linutronix.de>

On Tue, 2018-04-24 at 11:35 +0200, speck for Peter Zijlstra wrote:
> 
> Another option, that is being explored, is to co-schedule siblings.
> So ensure all siblings either run vcpus of the _same_ VM or idle.
> 
> Of course, this is all rather intrusive and ugly and brings with it
> setup costs as well, because you'd have to sync up on VMENTER, VMEXIT
> and interrupts (on the idle CPUs).

I hate to suggest more microcode hacks but... if there was an MSR bit
which, when set, would pause any HT sibling that was currently in VMX
non-root mode, then we could set that up to be automatically set on
vmexit and it would automatically pause the problematic siblings.
Meaning that co-ordinating vmexits with them might actually be
feasible?

The precise definition of 'pause' in the above could survive some
bikeshedding, but basically it shouldn't run any more guest
instructions, but it *should* be allowed to vmexit on interrupts, etc.