From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 28 Feb 2019 01:04:34 -0000 Received: from mx1.redhat.com ([209.132.183.28]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gzA7l-0001Sl-82 for speck@linutronix.de; Thu, 28 Feb 2019 02:04:33 +0100 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F15852BE84 for ; Thu, 28 Feb 2019 01:04:26 +0000 (UTC) Received: from treble (ovpn-120-232.rdu2.redhat.com [10.10.120.232]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9C94416924 for ; Thu, 28 Feb 2019 01:04:26 +0000 (UTC) Date: Wed, 27 Feb 2019 19:04:24 -0600 From: Josh Poimboeuf Subject: [MODERATED] Re: [patch V5 00/14] MDS basics 0 Message-ID: <20190228010424.dk273xj7qa7trvqr@treble> References: <20190227150939.605235753@linutronix.de> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Feb 27, 2019 at 10:04:33PM +0100, speck for Thomas Gleixner wrote: > On Wed, 27 Feb 2019, speck for Thomas Gleixner wrote: > > > Changes since V4: > > > > - Fix SSB whitelist. Needs to go upstream independently. > > > > - Consolidate whitelists before adding another one. > > > > - Use an inline helper for the exit to user mitigation. > > > > - Add VMX/VMENTER mitigation when CPU is not affected by L1TF. > > > > - Remove 'auto' command line option. > > > > - Rework the mitigation documentation so the handling of special > > exceptions is clear. > > > > - Adjust the virt mitigation admin documentation. > > > > - Fix typos and address review comments > > > > Available from git: > > > > cvs.ou.linutronix.de:linux/speck/linux WIP.mds > > Pushed out a new tree which contains the fixups for the consolidated table > and the documentation for VMX. > > Delta patch below. Your last update had a bunch of issues: didn't compile, missing entries, typos, whitespace. The below fixed it for me (on top of your bad patch): diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 7b34ac46f4db..0558e9ee1fec 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -955,39 +955,40 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) #define NO_MDS BIT(4) #define VULNWL(vendor, family, model, whitelist) \ - { X86_VENDOR_##vendor, number, model, X86_FEATURE_ANY, whitelist) + { X86_VENDOR_##vendor, family, model, X86_FEATURE_ANY, whitelist } static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { - VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION }, - VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION }, - VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION }, - VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL, NO_SPECULATION }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_TABLET, NO_SPECULATION }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_MID, NO_SPECULATION }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_BONELL, NO_SPECULATION }, - - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT, NO_SSB | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_, NO_SSB | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT, NO_SSB | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_CORE_YONAH, NO_SSB | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNL, NO_SSB | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNM, NO_SSB | NO_L1TF }, - - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, NO_MDS | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X, NO_MDS | NO_L1TF }, - VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF }, - - VULNWL(AMD, 0x0f, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF }, - VULNWL(AMD, 0x10, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF }, - VULNWL(AMD, 0x11, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF }, - VULNWL(AMD, 0x12, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF }, + VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), + VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), + VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), + VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL, NO_SPECULATION), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_TABLET, NO_SPECULATION), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_MID, NO_SPECULATION), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_BONNELL, NO_SPECULATION), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_BONNELL_MID, NO_SPECULATION), + + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT, NO_SSB | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X, NO_SSB | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT, NO_SSB | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_CORE_YONAH, NO_SSB | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNL, NO_SSB | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNM, NO_SSB | NO_L1TF), + + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, NO_MDS | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X, NO_MDS | NO_L1TF), + VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF), + + VULNWL(AMD, 0x0f, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF), + VULNWL(AMD, 0x10, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF), + VULNWL(AMD, 0x11, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF), + VULNWL(AMD, 0x12, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF), /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ - VULNWL(AMD, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF }, - VULNWL(HYGON, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF }, + VULNWL(AMD, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF), + VULNWL(HYGON, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF), {} };