From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 28 Feb 2019 08:11:14 -0000 Received: from mail.kernel.org ([198.145.29.99]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gzGme-0006yx-Io for speck@linutronix.de; Thu, 28 Feb 2019 09:11:13 +0100 Date: Thu, 28 Feb 2019 09:11:03 +0100 From: Greg KH Subject: [MODERATED] Re: [patch V5 08/14] MDS basics 8 Message-ID: <20190228081103.GA23993@kroah.com> References: <20190227150939.605235753@linutronix.de> <20190227152037.728148331@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20190227152037.728148331@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Feb 27, 2019 at 04:09:47PM +0100, speck for Thomas Gleixner wrote: > CPUs which are affected by L1TF and MDS mitigate MDS with the L1D Flush on > VMENTER when updated microcode is installed. CPUs which are not affected by > L1TF but affected by MDS need explicit MDS mitigation. > > For these cases, follow the host mitigation state and invoke the MDS > mitigation before VMENTER. > > Signed-off-by: Thomas Gleixner Reviewed-by: Greg Kroah-Hartman