From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 01 Mar 2019 22:00:38 -0000 Received: from mga17.intel.com ([192.55.52.151]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gzqCq-0004yz-Fz for speck@linutronix.de; Fri, 01 Mar 2019 23:00:36 +0100 Date: Fri, 1 Mar 2019 14:00:33 -0800 From: mark gross Subject: [MODERATED] Re: [patch V5 12/14] MDS basics 12 Message-ID: <20190301220033.GA24427@mgross-MOBL.amr.corp.intel.com> Reply-To: mgross@linux.intel.com References: <20190227150939.605235753@linutronix.de> <20190227152038.103543344@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190227152038.103543344@linutronix.de> To: speck@linutronix.de Cc: dave@sr71.net List-ID: On Wed, Feb 27, 2019 at 04:09:51PM +0100, speck for Thomas Gleixner wrote: > Subject: [patch V5 12/14] x86/speculation/mds: Add mitigation mode VMWERV > From: Thomas Gleixner > > In virtualized environments it can happen that the host has the microcode > update which utilizes the VERW instruction to clear CPU buffers, but the > hypervisor is not yet updated to expose the X86_FEATURE_MD_CLEAR CPUID bit > to guests. > > Introduce an internal mitigation mode VWWERV which enables the invocation ^VMWERV --mark