From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 23 Sep 2019 12:47:15 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iCNkH-0004K8-Me for speck@linutronix.de; Mon, 23 Sep 2019 14:47:14 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id F1093ACCA for ; Mon, 23 Sep 2019 12:47:05 +0000 (UTC) Date: Mon, 23 Sep 2019 14:47:05 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH v4 01/10] TAAv4 1 Message-ID: <20190923124705.GB13719@zn.tnic> References: =?utf-8?q?=3Ca1198a67dac0fbb2c7adeafff91499e1396f51d4=2E1567543894=2Egi?= =?utf-8?q?t=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?= MIME-Version: 1.0 In-Reply-To: =?utf-8?q?=3Ca1198a67dac0fbb2c7adeafff91499e1396f51d4=2E15675?= =?utf-8?q?43894=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Tue, Sep 03, 2019 at 02:11:32PM -0700, speck for Pawan Gupta wrote: > From: Pawan Gupta > Subject: [PATCH v4 01/10] x86/tsx: Add enumeration support for IA32_TSX_CTRL > MSR >=20 > Transactional Synchronization Extensions (TSX) may be used on certain > processors as part of a speculative side channel attack. A microcode > update for existing processors that are vulnerable to this attack will > add a new MSR, IA32_TSX_CTRL to allow the system administrator the option > to disable TSX as one of the possible mitigations. [Note that future > processors that are not vulnerable will also support the IA32_TSX_CTRL > MSR]. This patch adds the defines for the new IA32_TSX_CTRL MSR and its Avoid having "This patch" or "This commit" in the commit message. It is tautologically useless. Also, do $ git grep 'This patch' Documentation/process for more details. > bits. >=20 > Bit 7 of the IA32_ARCH_CAPABILITIES indicates the presence of the > IA32_TSX_CTRL MSR. >=20 > There are two control bits in IA32_TSX_CTRL MSR: >=20 > Bit 0: Can be written to "1" to disable the Restricted Transactional "Bit 0: When set, it disables ... " > Memory (RTM) sub-feature of TSX (will force all transactions > to abort on the XBEGIN instruction). >=20 > Bit 1: Can be written to "1" to disable enumeration of the RTM feature Ditto. > (i.e. will make CPUID(EAX=3D7).EBX{bit11} read as 0). >=20 > The other TSX sub-feature, Hardware Lock Elision (HLE), is unconditionally > disabled but still enumerated as present by CPUID(EAX=3D7).EBX{bit4}. >=20 > Signed-off-by: Pawan Gupta > --- > arch/x86/include/asm/msr-index.h | 5 +++++ > 1 file changed, 5 insertions(+) >=20 > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h > index 271d837d69a8..9163eb67962e 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -93,6 +93,7 @@ > * Microarchitectural Data > * Sampling (MDS) vulnerabilities. > */ > +#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available.= */ > =20 > #define MSR_IA32_FLUSH_CMD 0x0000010b > #define L1D_FLUSH BIT(0) /* > @@ -103,6 +104,10 @@ > #define MSR_IA32_BBL_CR_CTL 0x00000119 > #define MSR_IA32_BBL_CR_CTL3 0x0000011e > =20 > +#define MSR_IA32_TSX_CTRL 0x00000122 > +#define MSR_TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ > +#define MSR_TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ For those last two: s/MSR_// Thx. --=20 Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imend=C3=B6rffer, HRB 247165,= AG M=C3=BCnchen --=20