From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 26 Sep 2019 02:34:59 -0000 Received: from mx1.redhat.com ([209.132.183.28]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iDJcN-0006AV-Je for speck@linutronix.de; Thu, 26 Sep 2019 04:34:58 +0200 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 319AC307D98A for ; Thu, 26 Sep 2019 02:34:48 +0000 (UTC) Received: from treble (ovpn-120-76.rdu2.redhat.com [10.10.120.76]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D54D619C68 for ; Thu, 26 Sep 2019 02:34:47 +0000 (UTC) Date: Wed, 25 Sep 2019 21:34:45 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: [PATCH v4 03/10] TAAv4 3 Message-ID: <20190926023445.afjeaizeloehi6bn@treble> References: <5b6df5ee-a5b7-c281-de29-af6544b8abb6@intel.com> <20190906074645.GE13480@guptapadev.amr> <20190925224817.zcmzswojw5tmymul@treble> <20190926011305.GD16811@guptapadev.amr> MIME-Version: 1.0 In-Reply-To: <20190926011305.GD16811@guptapadev.amr> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Sep 25, 2019 at 06:13:05PM -0700, speck for Pawan Gupta wrote: > > > > > +static int __init tsx_cmdline(char *str) > > > > > +{ > > > > > + if (!str) > > > > > + return -EINVAL; > > > > > + > > > > > + if (!strcmp(str, "on")) > > > > > + tsx_ctrl_state = TSX_CTRL_ENABLE; > > > > > + else if (!strcmp(str, "off")) > > > > > + tsx_ctrl_state = TSX_CTRL_DISABLE; > > > > > + > > > > > + return 0; > > > > > +} > > > > > +early_param("tsx", tsx_cmdline); > > > > > > > > Hmm... Let's say I have a non-TSX system. I specify tsx=on. This will > > > > set tsx_ctrl_state=TSX_CTRL_ENABLE, then tsx_ctrl_check_support() will > > > > set it to tsx_ctrl_state=TSX_CTRL_NOT_SUPPORTED. > > > > > > > > I *think* this all works, but I'd love a comment or two about it. Maybe > > > > even something that makes it clear that tsx_en/disable() are both only > > > > called when TSX *AND* TSX_CTRL_MSR are supported. > > > > > > > > This is all kinda weird and confusing because we're doing this all > > > > without the X86_FEATURE bits for TSX. > > > > > > If we add another X86_FEATURE bit it will have exact same state as > > > X86_FEATURE_RTM. Do we really need this? > > > > How about moving the tsx_init() call to early_init_intel()? Then you'd > > be able to check the feature bit above. And that might make the > > ordering a little easier to follow. > > Sorry, I am failing to understand how it would make a difference. > early_init_intel() is also called from init_init(). Regardless, shouldn't tsx_init() at least be called before cpu_set_bug_bits(), so that X86_BUG_TAA can get set appropriately? In that case, instead of early_param(), tsx_init() could just use cmdline_find_option() to find the 'tsx=' option. That would also have the advantage of making it much easier to untangle the initialization order. If early_init_intel() isn't the right spot, then maybe early_identify_cpu(). -- Josh