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From: "Luck, Tony" <tony.luck@intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v6 1/9] TAAv6 1
Date: Thu, 10 Oct 2019 09:51:04 -0700	[thread overview]
Message-ID: <20191010165104.GA11981@agluck-desk2.amr.corp.intel.com> (raw)
In-Reply-To: <c6e22bfb-578a-07b7-231f-854e540e3ac7@citrix.com>

On Thu, Oct 10, 2019 at 01:01:38AM +0100, speck for Andrew Cooper wrote:
> On 10/10/2019 00:53, speck for Luck, Tony wrote:
> > On Thu, Oct 10, 2019 at 12:40:45AM +0100, speck for Andrew Cooper wrote:
> >>> I don't know what the enabled status of HLE is on the MDS_NO, TAA parts,
> >>> and whether it is statically disabled with the TSX_CTRL microcode, but
> >>> if it isn't statically disabled then it needs to be dynamically disabled
> >>> by bit 0, or a 'CLFLUSH; XBEGIN ...; MOV secret' can still be used to
> >>> exploit TAA.
> >> Apologies.  That is the RTM sequence.
> >>
> >> For HLE, I meant 'CLFLUSH; XAQUIRE ...; MOV secret'.
> > Did we send out a review copy of the white paper for TAA yet?
> 
> Not as far as I am aware.  Have I missed something?

May just be that we haven't shared it yet.

> I'm still working from the ppdf from June 26th, which I seem to recall
> was from just after the adjustment of bit 0's behaviour away from
> causing #UD's.
> 
> > HLE is kind of buried, but we do say:
> >
> >    On processors that enumerate IA32_ARCH_CAPABILITIES[TSX_CTRL]
> >    (bit 7)=1, HLE prefix hints are always ignored.
> >
> > Which is to say that HLE is unconditionally disabled by the
> > new microcode for TAA.
> 
> Great.  I look forward to a paper to review.
> 
> Is that a firm decision on Ronak's suggestion that HLE is going to be
> sunset?

I think so ... I believe that is why the somewhat awkward wording
above (trying to cover case for existing CPUs that will get a microcode
update to implement TSX_CTRL and also future ones that have that from
the get go).

-Tony

  reply	other threads:[~2019-10-10 16:51 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-09 23:21 [MODERATED] [PATCH v6 0/9] TAAv6 0 Pawan Gupta
2019-10-09 23:22 ` [MODERATED] [PATCH v6 1/9] TAAv6 1 Pawan Gupta
2019-10-09 23:23 ` [MODERATED] [PATCH v6 2/9] TAAv6 2 Pawan Gupta
2019-10-09 23:24 ` [MODERATED] [PATCH v6 3/9] TAAv6 3 Pawan Gupta
2019-10-09 23:25 ` [MODERATED] [PATCH v6 4/9] TAAv6 4 Pawan Gupta
2019-10-09 23:26 ` [MODERATED] [PATCH v6 5/9] TAAv6 5 Pawan Gupta
2019-10-09 23:27 ` [MODERATED] [PATCH v6 6/9] TAAv6 6 Pawan Gupta
2019-10-09 23:28 ` [MODERATED] [PATCH v6 7/9] TAAv6 7 Pawan Gupta
2019-10-09 23:29 ` [MODERATED] [PATCH v6 8/9] TAAv6 8 Pawan Gupta
2019-10-09 23:30 ` [MODERATED] [PATCH v6 9/9] TAAv6 9 Pawan Gupta
2019-10-09 23:34 ` [MODERATED] Re: [PATCH v6 1/9] TAAv6 1 Pawan Gupta
2019-10-10  1:23   ` Pawan Gupta
2019-10-15 12:54     ` Thomas Gleixner
2019-10-21 20:35       ` [MODERATED] " Pawan Gupta
2019-10-09 23:38 ` Andrew Cooper
2019-10-09 23:40   ` Andrew Cooper
2019-10-09 23:53     ` Luck, Tony
2019-10-10  0:01       ` Andrew Cooper
2019-10-10 16:51         ` Luck, Tony [this message]
     [not found] ` <5d9e6daa.1c69fb81.f84ad.88ceSMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-10  6:47   ` [MODERATED] Re: [PATCH v6 3/9] TAAv6 3 Greg KH
2019-10-10 23:44     ` Pawan Gupta
     [not found] ` <5d9e6e22.1c69fb81.6df19.ff55SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-10  6:50   ` [MODERATED] Re: [PATCH v6 5/9] TAAv6 5 Greg KH
2019-10-10 21:18     ` Pawan Gupta
2019-10-10  6:50   ` Greg KH
     [not found] ` <5d9e6f13.1c69fb81.d7036.be99SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-10  6:54   ` [MODERATED] Re: [PATCH v6 9/9] TAAv6 9 Greg KH
2019-10-12  1:41     ` Pawan Gupta
2019-10-13 20:05       ` Ben Hutchings
2019-10-13 21:00         ` Ben Hutchings
     [not found] ` <4b15283c29b75be3177eb7c4b8601be5644f630e.157065=?utf-8?q?8889?= .git.pawan.kumar.gupta@linux.intel.com>
2019-10-18  1:21   ` [MODERATED] Re: [PATCH v6 8/9] TAAv6 8 Ben Hutchings
2019-10-21 20:04 ` [MODERATED] Re: [PATCH v6 0/9] TAAv6 0 Josh Poimboeuf
2019-10-21 20:09   ` Pawan Gupta

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