From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 16 Oct 2019 18:40:22 -0000 Received: from mga03.intel.com ([134.134.136.65]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iKoDd-0002UD-5K for speck@linutronix.de; Wed, 16 Oct 2019 20:40:22 +0200 Date: Wed, 16 Oct 2019 11:34:17 -0700 From: Pawan Gupta Subject: [MODERATED] Re: [PATCH v5 08/11] TAAv5 8 Message-ID: <20191016183417.GA18093@guptapadev.amr> References: <20191014210458.GF4957@zn.tnic> <20191015103454.GW317@dhcp22.suse.cz> <20191016075434.GL317@dhcp22.suse.cz> <20191016092333.GQ317@dhcp22.suse.cz> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Oct 16, 2019 at 02:15:08PM +0200, speck for Thomas Gleixner wrote: > On Wed, 16 Oct 2019, speck for Michal Hocko wrote: > > On Wed 16-10-19 09:54:34, speck for Michal Hocko wrote: > > [...] > > > +config X86_INTEL_TSX_MODE_OFF > > > + bool "off" > > > + help > > > + TSX is always disabled - equals tsx=off command line parameter. > > > + > > > +config X86_INTEL_TSX_MODE_ON > > > + bool "on" > > > + help > > > + TSX is always enabled on TSX capable HW - equals tsx=on command line > > > + parameter. > > > + > > > +config X86_INTEL_TSX_MODE_AUTO > > > + bool "auto" > > > + help > > > + TSX is enabled on TSX capable HW that is believed to be safe against > > > + side channel attacks- equals tsx=auto command line parameter. > > > +endchoice > > > > I have just reread the discussion again and I have to say that there is > > more confusion and uncertainty than I would like to see. Can somebody > > from Intel give an authoritative answer to the following question > > please? > > > > Is tsx=auto going to lead to any different state than tsx=on? In other > > words does auto mode make any sense at all? > > Is it only my vacation induced spark of mental sanity or is this whole TAA > thing a complete trainwreck again? > > We're at version 5 and more than 3 month since the first RFC got posted and > we are still debating which CPUs are affected and which migitations are > going to be deployed depending on the CPU advertized misfeatures and the > eventually surfacing microcode? > > Can we please stop this complete waste of time right now and start over > with clarifying the situation? I.e. someone at Intel needs to sit down and > write up a matrix: > > TAA-Affected | MDS_NO | VERW works | TSX_MSR | Resulting action > -------------|--------|------------|---------|----------------- > No | X | X | Y | ? > No | X | X | N | None > Yes | 0 | 0 | 0 | SNAFU > ... | | | | > > You surely can fill in the rest on your own, right? > > And exactly that information wants to be in the admin documentation or in a > separate Documentation/x86/taa.rst as well. I am working on this with other folks at Intel. Thanks, Pawan