From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 22 Oct 2019 00:41:05 -0000 Received: from mga14.intel.com ([192.55.52.115]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMiES-0005u4-BK for speck@linutronix.de; Tue, 22 Oct 2019 02:41:04 +0200 Date: Mon, 21 Oct 2019 17:34:52 -0700 From: Pawan Gupta Subject: [MODERATED] Re: [PATCH v7 00/10] TAAv7 0 Message-ID: <20191022003452.GE23497@guptapadev.amr> References: MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Mon, Oct 21, 2019 at 02:32:31PM -0700, speck for Andy Lutomirski wrote: > On 10/21/19 1:22 PM, speck for Pawan Gupta wrote: > > From: Pawan Gupta > > Subject: [PATCH v7 00/10] TAAv7 > > > > Changes since v6: > > - Add Michal's patch to allow tsx=on|off|auto via CONFIG > > - Rebase to v5.4-rc4 > > - Changelog, comments and documentation update. > > > > Changes since v5: > > - Remove unsafe X86_FEATURE_RTM toggles. > > I'm wondering if maybe these patches shouldn't touch the cpu > capabilities at all. After all, even with TSX toggled off, TSX is still > present -- XBEGIN doesn't give #UD. By making this change, we avoid > needing to even consider what happens when a cpu capability bit changes > after boot. This would affect some of the PMU related boot_cpu_has() checks. https://elixir.bootlin.com/linux/latest/source/arch/x86/events/intel/core.c#L3415 > > I think it would be nice to expose whether TSX is enabled somewhere in > sysfs, but I'm not convinced that "features" is the place for it. Part 10/10 in this series adds support to expose whether TSX is enabled (only present when TSX_CTRL MSR is supported): $ cat /sys/devices/system/cpu/hw_tx_mem Thanks, Pawan