From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 22 Oct 2019 08:00:48 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMp5z-0001yk-M7 for speck@linutronix.de; Tue, 22 Oct 2019 10:00:47 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id E4B1EB12D for ; Tue, 22 Oct 2019 08:00:41 +0000 (UTC) Date: Tue, 22 Oct 2019 10:00:41 +0200 From: Michal Hocko Subject: [MODERATED] Re: ***UNCHECKED*** [PATCH v7 09/10] TAAv7 9 Message-ID: <20191022080041.GY9379@dhcp22.suse.cz> References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Mon 21-10-19 13:31:02, speck for Michal Hocko wrote: [...] > +config X86_INTEL_TSX_MODE_ON > + bool "on" > + help > + TSX is always enabled on TSX capable HW - equals tsx=on command line > + parameter. > + > +config X86_INTEL_TSX_MODE_AUTO > + bool "auto" > + help > + TSX is enabled on TSX capable HW that is believed to be safe against > + side channel attacks- equals tsx=auto command line parameter. Considering how small the list of CPUs that make a difference for the two modes please add those models here as well. -- Michal Hocko SUSE Labs