From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 22 Oct 2019 08:15:43 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMpKO-0002a1-PB for speck@linutronix.de; Tue, 22 Oct 2019 10:15:42 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id BA75EAC83 for ; Tue, 22 Oct 2019 08:15:34 +0000 (UTC) Date: Tue, 22 Oct 2019 10:15:34 +0200 From: Michal Hocko Subject: [MODERATED] Re: ***UNCHECKED*** [PATCH v7 03/10] TAAv7 3 Message-ID: <20191022081534.GA9379@dhcp22.suse.cz> References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Mon 21-10-19 13:25:02, speck for Pawan Gupta wrote: [...] > + tsx= [X86] Control Transactional Synchronization > + Extensions (TSX) feature in Intel processors that > + support TSX control. > + > + This parameter controls the TSX feature. The options are: > + > + on - Enable TSX on the system. > + off - Disable TSX on the system. Please explicitly mention that off is active only if TSX there is ucode support for that (aka MSR_IA32_TSX_CTRL). -- Michal Hocko SUSE Labs