From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 22 Oct 2019 17:01:21 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMxX5-0002XQ-Ie for speck@linutronix.de; Tue, 22 Oct 2019 19:01:20 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id F3ADEB4D4 for ; Tue, 22 Oct 2019 17:01:13 +0000 (UTC) Date: Tue, 22 Oct 2019 19:01:13 +0200 From: Michal Hocko Subject: [MODERATED] Re: ***UNCHECKED*** Re: [PATCH v7 03/10] TAAv7 3 Message-ID: <20191022170113.GU9379@dhcp22.suse.cz> References: <20191022081534.GA9379@dhcp22.suse.cz> <20191022144226.lbxywrikxwcjxjyf@treble> <20191022164801.GA29216@guptapadev.amr> MIME-Version: 1.0 In-Reply-To: <20191022164801.GA29216@guptapadev.amr> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Tue 22-10-19 09:48:01, speck for Pawan Gupta wrote: > On Tue, Oct 22, 2019 at 09:42:26AM -0500, speck for Josh Poimboeuf wrote: > > On Tue, Oct 22, 2019 at 10:15:34AM +0200, speck for Michal Hocko wrote: > > > On Mon 21-10-19 13:25:02, speck for Pawan Gupta wrote: > > > [...] > > > > + tsx= [X86] Control Transactional Synchronization > > > > + Extensions (TSX) feature in Intel processors that > > > > + support TSX control. > > > > + > > > > + This parameter controls the TSX feature. The options are: > > > > + > > > > + on - Enable TSX on the system. > > > > + off - Disable TSX on the system. > > > > > > Please explicitly mention that off is active only if TSX there is ucode > > > support for that (aka MSR_IA32_TSX_CTRL). > > > > I'm pretty sure I already asked for this in the last revision. And this > > is not the first time I've seen ignored feedback. Pawan, please try to > > take all feedback into account so we don't have to keep repeating > > ourselves. > > I am sorry to have missed it. All of the operation on|off|auto are > dependent on TSX control being present. The tsx= description states that > processors need TSX control support. I would extend it to specifically > say ucode update adds TSX control support (aka MSR_IA32_TSX_CTRL). Thanks! An explicit note about the MSR is important because that is something people can google for. > > tsx= [X86] Control Transactional Synchronization > Extensions (TSX) feature in Intel processors that > support TSX control. -- Michal Hocko SUSE Labs