From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 22 Oct 2019 17:26:53 -0000 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120] helo=us-smtp-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMxvn-0003TK-Sr for speck@linutronix.de; Tue, 22 Oct 2019 19:26:52 +0200 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 065C047B for ; Tue, 22 Oct 2019 17:26:47 +0000 (UTC) Received: from treble (ovpn-124-213.rdu2.redhat.com [10.10.124.213]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A992660C5E for ; Tue, 22 Oct 2019 17:26:46 +0000 (UTC) Date: Tue, 22 Oct 2019 12:26:44 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: [PATCH v7 01/10] TAAv7 1 Message-ID: <20191022172644.hyplx23aqpu7awxg@treble> References: =?utf-8?q?=3Cfc886d6e7492f33d2747d0f13cf4da97cec9a680=2E1571688957=2Egi?= =?utf-8?q?t=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?= MIME-Version: 1.0 In-Reply-To: =?utf-8?q?=3Cfc886d6e7492f33d2747d0f13cf4da97cec9a680=2E15716?= =?utf-8?q?88957=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Mon, Oct 21, 2019 at 01:23:02PM -0700, speck for Pawan Gupta wrote: > From: Pawan Gupta > Subject: [PATCH v7 01/10] x86/tsx: Add enumeration support for IA32_TSX_CTRL > MSR > > Transactional Synchronization Extensions (TSX) may be used on certain > processors as part of a speculative side channel attack. A microcode > update for existing processors that are vulnerable to this attack will > add a new MSR, IA32_TSX_CTRL to allow the system administrator the > option to disable TSX as one of the possible mitigations. [Note that > future processors that are not vulnerable will also support the > IA32_TSX_CTRL MSR]. This should clarify that not *all* TAA-vulnerable CPUs will get IA32_TSX_CTRL, instead only the ones which aren't vulnerable to MDS. -- Josh