From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 22 Oct 2019 17:35:18 -0000 Received: from us-smtp-1.mimecast.com ([205.139.110.61] helo=us-smtp-delivery-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMy3x-0003g3-92 for speck@linutronix.de; Tue, 22 Oct 2019 19:35:17 +0200 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 8AB221005509 for ; Tue, 22 Oct 2019 17:35:12 +0000 (UTC) Received: from treble (ovpn-124-213.rdu2.redhat.com [10.10.124.213]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 38AC860126 for ; Tue, 22 Oct 2019 17:35:12 +0000 (UTC) Date: Tue, 22 Oct 2019 12:35:10 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: ***UNCHECKED*** Re: [PATCH v7 03/10] TAAv7 3 Message-ID: <20191022173510.roy47kqyx6ssxjdv@treble> References: <20191022081534.GA9379@dhcp22.suse.cz> <20191022144226.lbxywrikxwcjxjyf@treble> <20191022164801.GA29216@guptapadev.amr> <20191022170113.GU9379@dhcp22.suse.cz> MIME-Version: 1.0 In-Reply-To: <20191022170113.GU9379@dhcp22.suse.cz> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Tue, Oct 22, 2019 at 07:01:13PM +0200, speck for Michal Hocko wrote: > On Tue 22-10-19 09:48:01, speck for Pawan Gupta wrote: > > On Tue, Oct 22, 2019 at 09:42:26AM -0500, speck for Josh Poimboeuf wrote: > > > On Tue, Oct 22, 2019 at 10:15:34AM +0200, speck for Michal Hocko wrote: > > > > On Mon 21-10-19 13:25:02, speck for Pawan Gupta wrote: > > > > [...] > > > > > + tsx= [X86] Control Transactional Synchronization > > > > > + Extensions (TSX) feature in Intel processors that > > > > > + support TSX control. > > > > > + > > > > > + This parameter controls the TSX feature. The options are: > > > > > + > > > > > + on - Enable TSX on the system. > > > > > + off - Disable TSX on the system. > > > > > > > > Please explicitly mention that off is active only if TSX there is ucode > > > > support for that (aka MSR_IA32_TSX_CTRL). > > > > > > I'm pretty sure I already asked for this in the last revision. And this > > > is not the first time I've seen ignored feedback. Pawan, please try to > > > take all feedback into account so we don't have to keep repeating > > > ourselves. > > > > I am sorry to have missed it. All of the operation on|off|auto are > > dependent on TSX control being present. The tsx= description states that > > processors need TSX control support. I would extend it to specifically > > say ucode update adds TSX control support (aka MSR_IA32_TSX_CTRL). > > Thanks! An explicit note about the MSR is important because that is > something people can google for. But as we've learned, most people won't know what that really means and how it relates to different CPU. This also needs to state in plain language that tsx=off only works for newer (MDS_NO) CPUs. The phrase 'off' is misleading, since it really means 'off on MDS_NO CPUs'. -- Josh