From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 23 Oct 2019 09:26:50 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNCun-0006fc-0v for speck@linutronix.de; Wed, 23 Oct 2019 11:26:49 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id A32EFB33A for ; Wed, 23 Oct 2019 09:26:42 +0000 (UTC) Date: Wed, 23 Oct 2019 11:26:33 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH v7 01/10] TAAv7 1 Message-ID: <20191023092633.GF12272@zn.tnic> References: <20191022172508.7h7d523puvepfjap@treble> MIME-Version: 1.0 In-Reply-To: <20191022172508.7h7d523puvepfjap@treble> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Tue, Oct 22, 2019 at 12:25:08PM -0500, speck for Josh Poimboeuf wrote: > How is HLE unconditionally disabled? Is it done by the above mentioned > microcode? Is there a way to enable it? >From patch 4: " TSX_CTRL_CPUID_CLEAR clears the RTM enumeration in CPUID. The other TSX sub-feature, Hardware Lock Elision (HLE), is unconditionally disabled with updated microcode but still enumerated as present by CPUID(EAX=3D7).EBX{bit4}." Sounds like the microcode zaps it but leaves the CPUID bit on. --=20 Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imend=C3=B6rffer, HRB 36809, = AG N=C3=BCrnberg --=20