From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 24 Oct 2019 16:19:40 -0000 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120] helo=us-smtp-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNfpr-0002OF-HQ for speck@linutronix.de; Thu, 24 Oct 2019 18:19:40 +0200 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 21E8B1007B2B for ; Thu, 24 Oct 2019 15:32:43 +0000 (UTC) Received: from treble (ovpn-121-225.rdu2.redhat.com [10.10.121.225]) by smtp.corp.redhat.com (Postfix) with ESMTPS id CB3505D9D5 for ; Thu, 24 Oct 2019 15:32:42 +0000 (UTC) Date: Thu, 24 Oct 2019 10:32:40 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: [PATCH 4/9] TAA 4 Message-ID: <20191024153240.26zdyr33r2o632ej@treble> References: <04f1ef8158e54eca18fc3951d75a00c5d398c429.1571905227.git.bp@suse.de> MIME-Version: 1.0 In-Reply-To: <04f1ef8158e54eca18fc3951d75a00c5d398c429.1571905227.git.bp@suse.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Oct 23, 2019 at 11:30:45AM +0200, speck for Pawan Gupta wrote: > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > index 885d4ac2111a..f8b8afc8f5b5 100644 > --- a/arch/x86/kernel/cpu/common.c > +++ b/arch/x86/kernel/cpu/common.c > @@ -1128,6 +1128,21 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) > if (!cpu_matches(NO_SWAPGS)) > setup_force_cpu_bug(X86_BUG_SWAPGS); > > + /* > + * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: > + * - TSX is supported or > + * - TSX_CTRL is present > + * > + * TSX_CTRL check is needed for cases when TSX could be disabled before > + * the kernel boot e.g. kexec. > + * TSX_CTRL check alone is not sufficient for cases when the microcode > + * update is not present or running as guest that don't get TSX_CTRL. > + */ > + if (!(ia32_cap & ARCH_CAP_TAA_NO) && > + (cpu_has(c, X86_FEATURE_RTM) || > + (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) > + setup_force_cpu_bug(X86_BUG_TAA); > + As I said before this would be a lot nicer if we could just add NO_TAA to the cpu_vuln_whitelist. -- Josh