From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 24 Oct 2019 17:34:37 -0000 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120] helo=us-smtp-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNh0N-0005Ml-TG for speck@linutronix.de; Thu, 24 Oct 2019 19:34:36 +0200 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CF7D41800E00 for ; Thu, 24 Oct 2019 17:34:31 +0000 (UTC) Received: from treble (ovpn-121-225.rdu2.redhat.com [10.10.121.225]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2345610027BF for ; Thu, 24 Oct 2019 17:34:30 +0000 (UTC) Date: Thu, 24 Oct 2019 12:34:28 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: [PATCH 4/9] TAA 4 Message-ID: <20191024173428.lxvl354phzasazlx@treble> References: <04f1ef8158e54eca18fc3951d75a00c5d398c429.1571905227.git.bp@suse.de> <20191024153240.26zdyr33r2o632ej@treble> <20191024164329.GE14115@zn.tnic> <20191024171543.5vnq6rik7bj2k7qo@treble> <20191024172356.GA14075@guptapadev.amr> MIME-Version: 1.0 In-Reply-To: <20191024172356.GA14075@guptapadev.amr> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Thu, Oct 24, 2019 at 10:23:56AM -0700, speck for Pawan Gupta wrote: > On Thu, Oct 24, 2019 at 12:15:43PM -0500, speck for Josh Poimboeuf wrote: > > On Thu, Oct 24, 2019 at 06:43:29PM +0200, speck for Borislav Petkov wrote: > > > On Thu, Oct 24, 2019 at 10:32:40AM -0500, speck for Josh Poimboeuf wrote: > > > > As I said before this would be a lot nicer if we could just add NO_TAA > > > > to the cpu_vuln_whitelist. > > > > > > We're waiting for a list of CPUs from Intel here, right? > > > > I guess so, unless somebody else can deduce that from existing > > information... > > This is the list to the best of my knowledge. > > +----------------------------+------------------+------------+ > | Name | Family / model | Stepping | > +============================+==================+============+ > | Whiskey Lake (ULT refresh) | 06_8E | 0xC | > +----------------------------+------------------+------------+ > | 2nd gen Cascade Lake | 06_55 | 6, 7 | > +----------------------------+------------------+------------+ > | Coffee Lake R | 06_9E | 0xD | > +----------------------------+------------------+------------+ That may be helpful, but I think the question is how does that information translate to the cpu_vuln_whitelist table. -- Josh