From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 24 Oct 2019 21:00:20 -0000 Received: from mga11.intel.com ([192.55.52.93]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNkDT-0001aQ-43 for speck@linutronix.de; Thu, 24 Oct 2019 23:00:19 +0200 Date: Thu, 24 Oct 2019 14:00:15 -0700 From: "Luck, Tony" Subject: [MODERATED] Re: [PATCH v7 06/10] TAAv7 6 Message-ID: <20191024210015.GA6231@agluck-desk2.amr.corp.intel.com> References: <5dae165e.1c69fb81.4beee.e271SMTPIN_ADDED_BROKEN@mx.google.com> <8a5f0e97-e258-b58b-2fb5-63f37d2d3abc@redhat.com> MIME-Version: 1.0 In-Reply-To: <8a5f0e97-e258-b58b-2fb5-63f37d2d3abc@redhat.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Thu, Oct 24, 2019 at 10:53:16PM +0200, speck for Paolo Bonzini wrote: > On the other hand, removing bits from CPUID or MSRs can cause issues > even if TSX is not enabled in VMs. Since most VMs won't have MDS_NO > set, I think we should drop this patch for now. After the embargo lifts > we can add code to pass TSX_CTRL to the VM just like we do for > SPEC_CTRL, including disabling TSX on vmentry/vmexit depending on guest > CPUID. TSX_CTRL is a slow MSR ... so if you do go this path you may also want some heuristic to avoid switching a thread between guests that have different settings for TSX. -Tony