From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 25 Oct 2019 07:18:04 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNtrG-0000qi-On for speck@linutronix.de; Fri, 25 Oct 2019 09:18:03 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id D70EFACC6 for ; Fri, 25 Oct 2019 07:17:55 +0000 (UTC) Date: Fri, 25 Oct 2019 09:17:47 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH 3/9] TAA 3 Message-ID: <20191025071746.GA22381@zn.tnic> References: <580e02757c3e639bff00fcea830aa46eba46a92f.1571905227.git.bp@suse.de> <6f1ab744-622c-179b-276b-5506b2fd9ae1@citrix.com> <20191024194503.GH14115@zn.tnic> <38430127-3ece-dc06-2264-6b3bc347b523@citrix.com> <20191024201748.GL14115@zn.tnic> <832cb284-9852-5cfe-b71c-c3a23b85adc5@citrix.com> MIME-Version: 1.0 In-Reply-To: <832cb284-9852-5cfe-b71c-c3a23b85adc5@citrix.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Thu, Oct 24, 2019 at 11:38:21PM +0100, speck for Andrew Cooper wrote: > I don't necessarily disagree, but the customers (who ultimately pay my > salary) want late microcode loading and livepatching, so we've delivered. Yeah, you guys promised too much. How do you deal with userspace using a feature and you wanna upgrade microcode which disables it? TSX might not be a good example here because feature bits disappearing is still ok, it doesn't fault but it would simply start aborting transactions unconditionally but what if it is a CPU feature which userspace is actively using and it disappears underneath its feet all of a sudden? Just upgrade the microcode and forget about it is not enough. I'm pretty sure you'll have to "dance". But hey, you can buy almost everything with money nowadays so... :-) > Skylake CPUs aren't getting TSX_CTRL, but force setting/clearing bits at > boot will affect later logic.=C2=A0 (Unless I'm being blind while reading t= he > patches, which is a distinct possibility). Yes, that's why I'm saying we should not blindly force set and clear bits but mirror what CPUID is telling us. At least wrt TSX. --=20 Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imend=C3=B6rffer, HRB 36809, = AG N=C3=BCrnberg --=20