From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 20 Apr 2020 14:30:53 -0000 Received: from mga18.intel.com ([134.134.136.126]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1jQXRj-0007Dd-EE for speck@linutronix.de; Mon, 20 Apr 2020 16:30:52 +0200 Received: from localhost (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id 1EDD16363 for ; Mon, 20 Apr 2020 14:30:46 +0000 (UTC) Date: Mon, 20 Apr 2020 07:30:46 -0700 From: mark gross Subject: [MODERATED] Re: Re: [PATCH 4/4] V8 more sampling fun 4 Message-ID: <20200420143046.GA23804@mtg-dev.jf.intel.com> Reply-To: mgross@linux.intel.com References: <20200416172021.rf4l55ci6leimccm@treble> <20200416174914.GH21456@zn.tnic> MIME-Version: 1.0 In-Reply-To: <20200416174914.GH21456@zn.tnic> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Thu, Apr 16, 2020 at 07:49:14PM +0200, speck for Borislav Petkov wrote: > On Thu, Apr 16, 2020 at 12:20:21PM -0500, speck for Josh Poimboeuf wrote: > > On Thu, Jan 30, 2020 at 11:12:02AM -0800, speck for mark gross wrote: > > > +The possible values contained in this file are: > > > + > > > + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D > > > + Not affected Processor not vulnerable > > > + Vulnerable Processor vulnerable and mitigation di= sabled > > > + Vulnerable: No microcode Processor vulnerable and microcode is = missing > > > + mitigation > > > + Mitigated: Microcode Processor is vulnerable and mitigation= is in > > > + effect. > > > + Not affected (TSX disabled) Processor is only vulnerable when TSX = is > > > + enabled while this system was booted w= ith TSX > > > + disabled. > > > + Unknown Running on virtual guest processor tha= t is > > > + affected but with no way to know if ho= st > > > + processor is mitigated or vulnerable. > > > + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D > >=20 > > This doesn't match the code. >=20 > How's that? >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Not affected Processor not vulnerable > Vulnerable Processor vulnerable and mitigation disabled > Vulnerable: No microcode Processor vulnerable and microcode is missi= ng > mitigation > Mitigation: Microcode Processor is vulnerable and mitigation is in > effect. > Mitigation: TSX disabled Processor is only vulnerable when TSX is > enabled while this system was booted with T= SX > disabled. > Unknown: Dependent on > hypervisor status Running on virtual guest processor that is > affected but with no way to know if host > processor is mitigated or vulnerable. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > --=20 > Regards/Gruss, > Boris. >=20 > SUSE Software Solutions Germany GmbH, GF: Felix Imend=C3=B6rffer, HRB 36809= , AG N=C3=BCrnberg > --=20 Boris,=20 from your emails it looks like you are putting together the final version. I have recently (this morning) found out I need to add another family model to the affected processor list. Do you have a branch I could use to make a foll= ow up patch too? (or if you are cool with me adding it to my local version and dealing with any minor fix ups let me know) thanks, --mark