From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 11 Mar 2020 16:02:02 -0000 Received: from mga02.intel.com ([134.134.136.20]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1jC3o0-0004JX-5D for speck@linutronix.de; Wed, 11 Mar 2020 17:02:01 +0100 Received: from mtg-dev (mtg-dev.jf.intel.com [10.54.74.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.ostc.intel.com (Postfix) with ESMTPS id 94A5F636D for ; Wed, 11 Mar 2020 16:01:53 +0000 (UTC) Received: from mgross by mtg-dev with local (Exim 4.90_1) (envelope-from ) id 1jC3nt-000KL3-3H for speck@linutronix.de; Wed, 11 Mar 2020 09:01:53 -0700 Message-Id: =?utf-8?q?=3Cb3ce08567ed48062f9d1e0f166cc35afce7316af=2E158394?= =?utf-8?q?1169=2Egit=2Emgross=40linux=2Eintel=2Ecom=3E?= In-Reply-To: References: From: mark gross Date: Thu, 30 Jan 2020 11:12:02 -0800 Subject: [MODERATED] [PATCH 2/2] v3 more sampling fun 2 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 To: speck@linutronix.de List-ID: From: mark gross Subject: [PATCH 2/2] x86/speculation: SRBDS vulnerability and mitigation documentation Adds documentation for the SRBDS vulnerability and its mitigation. Reviewed-by: Tony Luck Signed-off-by: Mark Gross --- Documentation/admin-guide/hw-vuln/index.rst | 2 + .../special-register-buffer-data-sampling.rst | 145 ++++++++++++++++++ 2 files changed, 147 insertions(+) create mode 100644 Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst diff --git a/Documentation/admin-guide/hw-vuln/index.rst b/Documentation/admin-guide/hw-vuln/index.rst index 0795e3c2643f..99d5b3244ef9 100644 --- a/Documentation/admin-guide/hw-vuln/index.rst +++ b/Documentation/admin-guide/hw-vuln/index.rst @@ -14,3 +14,5 @@ are configurable at compile, boot or run time. mds tsx_async_abort multihit.rst + special-register-buffer-data-sampling.rst + diff --git a/Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst b/Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst new file mode 100644 index 000000000000..5acc7748f8e9 --- /dev/null +++ b/Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst @@ -0,0 +1,145 @@ +.. SPDX-License-Identifier: GPL-2.0 + +SRBDS - Special Register Buffer Data Sampling +====================================== + +SRBDS is a hardware vulnerability that allows MDS techniques to infer values +returned from special register accesses. Special register accesses are +accesses to off core registers. According to Intels evaluation, the special +register reads that have a security expectation of privacy are: +RDRAND, RDSEED and SGX EGETKEY. + +When RDRAND and RDSEED instructions are used the data is moved to the core +through the special register mechanism. + +Affected processors +-------------------- +Core models (desktop, mobile, Xeon-E3) that implement RDRAND and/or RDSEED and +are vulnerable to MFBDS (Micro architectural Fill Buffer Data Sampling) variant +of MDS (Micro architectural Data Sampling) or to TAA (TSX Asynchronous Abort) +when TSX is enabled, + + ============= ============ ======== + common name Family_Model Stepping + ============= ============ ======== + Ivybridge 06_3AH All + + Haswell 06_3CH All + Haswell_L 06_45H All + Haswell_G 06_46H All + + Broadwell_G 06_47H All + Broadwell 06_3DH All + + Skylake_L 06_4EH All + Skylake 06_5EH All + + Kabylake_L 06_8EH <=A + Kabylake_L 06_8EH 0xB only if TSX is enabled + Kabylake_L 06_8EH 0xC only if TSX is enabled + + Kabylake 06_9EH <=B + Kabylake 06_9EH 0xC only if TSX is enabled + Kabylake 06_9EH 0xD only if TSX is enabled + ============= ============ ======== + +Related CVEs +------------ + +The following CVE entry is related to this SRBDS issue: + + ============== ===== =================================================== + CVE-2020--0543 + ============== ===== =================================================== + +Attack scenarios +--------------- +An unprivileged user can extract returned values from RDRAND and RDSEED +executed on another core or sibling thread using MDS techniques. + + +Mitigtion mechanism +------------------- +Intel will release microcode updates that modify the RDRAND, RDSEED, and +EGETKEY instructions to overwrite secret special register data in the shared +staging buffer before the secret data can be accessed by another logical +processor. + +During execution of the RDRAND, RDSEED, or EGETKEY instruction, off-core +accesses from other logical processors will be delayed until the special +register read is complete and the secret data in the shared staging buffer is +overwritten. + +This has three effects on performance: +1 RDRAND, RDSEED, or EGETKEY instruction have higher latency. +2 Executing RDRAND at the same time on multiple logical processors will be + serialized, resulting in an overall reduction in the maximum RDRAND bandwidth. +3 Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other + logical processors that miss their core caches, with an impact similar to + legacy locked cache-line-split accesses. + +Because of the performance impact of the mitigation, the microcode updates also +provide an opt-out mechanism (RNGDS_MITG_DIS) to disable the mitigation for +RDRAND and RDSEED instructions executed outside of Intel Software Guard +Extensions (Intel SGX) enclaves. On logical processors that disable the +mitigation using this opt-out mechanism, RDRAND and RDSEED do not take longer +to execute and do not impact performance of sibling logical processors memory +accesses. The opt-out mechanism does not affect Intel SGX enclaves (including +execution of RDRAND or RDSEED inside of an enclave, as well as EGETKEY +execution). + +IA32_MCU_OPT_CTRL MSR Definition +-------------------------------- +Along with the mitigation for this issue, Intel added a new thread-scope +IA32_MCU_OPT_CTRL MSR, (address 0x123). The presence of this MSR and +RNGDS_MITG_DIS (bit 0) is enumerated by CPUID.(EAX=07H,ECX=0).EDX[SRBDS_CTRL = +9]==1. This MSR is introduced through the microcode update. + +Setting IA32_MCU_OPT_CTRL[0] (RNGDS_MITG_DIS) to 1 for a logical processor +disables the mitigation for RDRAND and RDSEED executed outside of an Intel SGX +enclave on that logical processor. Opting out of the mitigation for a +particular logical processor does not affect the RDRAND and RDSEED mitigations +for other logical processors. + +Note that inside of an Intel SGX enclave, the mitigation is applied regardless +of the value of RNGDS_MITG_DS. + +Mitigation control on the kernel command line +--------------------------------------------- +The kernel command line allows for control over the SRBDS mitigation at boot +time with the option "srbds=". The option for this is: + + ============= ============================================================ + off This option disables SRBS mitigation for RDRAND and RDSEED on + affected platforms. + ============= ============================================================ + +SRBS System Information +----------------------- +The Linux kernel provides vulnerability status information through sysfs. For +SRBDS this can be accessed by the following sysfs file: +/sys/devices/system/cpu/vulnerabilities/special_register_data_sampling + +The possible values contained in this file are: + + ============================== =========================================== + Not affected Processor not vulnerable + Vulnerable Processor vulnerable and mitigation disabled + Vulnerable: no microcode Processor vulnerable and microcode is missing + mitigation + Mitigated Processor is vulnerable and mitigation is in + effect. + Not affected (TSX disabled) Processor is only vulnerable when TSX is + enabled while this system was booted with TSX + disabled. + Unknown Running on virtual guest processor that is + affected but with no way to know if host + processor is mitigated or vulnerable. + ============================== =========================================== + +Default mitigations +------------------- +This new microcode serializes processor access during execution of RDRAND, +RDSEED ensures that the shared buffer is overwritten before it is released for +reuse. + -- 2.17.1