From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 25 Oct 2019 08:48:12 -0000 Received: from us-smtp-2.mimecast.com ([207.211.31.81] helo=us-smtp-delivery-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNvGV-0002wv-BG for speck@linutronix.de; Fri, 25 Oct 2019 10:48:11 +0200 Received: by mail-wm1-f69.google.com with SMTP id x23so732136wmj.7 for ; Fri, 25 Oct 2019 01:48:07 -0700 (PDT) Received: from [192.168.10.150] ([93.56.166.5]) by smtp.gmail.com with ESMTPSA id r2sm1801493wma.1.2019.10.25.01.48.05 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Oct 2019 01:48:05 -0700 (PDT) Subject: [MODERATED] Re: ***UNCHECKED*** [PATCH v7 3/5] NX 3 References: <1571934870-34323-1-git-send-email-pbonzini@redhat.com> <1571934870-34323-4-git-send-email-pbonzini@redhat.com> <20191025083739.GC7069@suse.de> From: Paolo Bonzini Message-ID: Date: Fri, 25 Oct 2019 10:48:04 +0200 MIME-Version: 1.0 In-Reply-To: <20191025083739.GC7069@suse.de> Content-Type: multipart/mixed; boundary="7hLlTn2Q0Gq6iUfJbMvuZLd5iankNpUml"; protected-headers="v1" To: speck@linutronix.de List-ID: This is an OpenPGP/MIME encrypted message (RFC 4880 and 3156) --7hLlTn2Q0Gq6iUfJbMvuZLd5iankNpUml Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 25/10/19 10:37, speck for Joerg Roedel wrote: > I fixed it with this diff: >=20 > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index e7970a2e8eae..6e9380a0ca41 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -997,7 +997,7 @@ static bool update_transition_efer(struct vcpu_vmx = *vmx, int efer_offset) > * On CPUs that support "load IA32_EFER", always switch EFER > * atomically, since it's faster than switching it manually. > */ > - if (cpu_has_load_ia32_efer() || > + if ((cpu_has_load_ia32_efer() && (guest_efer & EFER_NX)) || > (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { > if (!(guest_efer & EFER_LMA)) > guest_efer &=3D ~EFER_LME; >=20 What about this instead (completely untested): diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index e7970a2e8eae..1f923dee99e5 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -992,6 +992,9 @@ static bool update_transition_efer(struct vcpu_vmx *v= mx, int efer_offset) ignore_bits &=3D ~(u64)EFER_SCE; #endif =20 + guest_efer &=3D ~ignore_bits; + guest_efer |=3D host_efer & ignore_bits; + /* * On EPT, we can't emulate NX, so we must switch EFER atomically. * On CPUs that support "load IA32_EFER", always switch EFER @@ -1010,9 +1013,6 @@ static bool update_transition_efer(struct vcpu_vmx = *vmx, int efer_offset) } else { clear_atomic_switch_msr(vmx, MSR_EFER); =20 - guest_efer &=3D ~ignore_bits; - guest_efer |=3D host_efer & ignore_bits; - vmx->guest_msrs[efer_offset].data =3D guest_efer; vmx->guest_msrs[efer_offset].mask =3D ~ignore_bits; =20 --7hLlTn2Q0Gq6iUfJbMvuZLd5iankNpUml--