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Date: Wed, 27 Feb 2019 19:13:53 +0100 (CET)
From: Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [patch V5 00/14] MDS basics 0
In-Reply-To: <alpine.DEB.2.21.1902271850110.1644@nanos.tec.linutronix.de>
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References: <20190227150939.605235753@linutronix.de>
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To: speck@linutronix.de
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On Wed, 27 Feb 2019, speck for Thomas Gleixner wrote:
> On Wed, 27 Feb 2019, speck for Linus Torvalds wrote:
> > and then the lines are at least a bit shorter:
> > 
> >         VULN_WHITELIST(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
> > 
> > (or do we actually need the feature mask? None of the existing cases
> > seem to have it?)
> 
> No. I just had to add it to be able to use driver_data.
> 
> > I dunno. Maybe none of this matters.
> 
> Lemme have a try.

Something like this:

#define VULNWL(vendor, family, model, whitelist)        \
        { X86_VENDOR_##vendor, number, model, X86_FEATURE_ANY, whitelist)

static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
        VULNWL(ANY,     4, X86_MODEL_ANY,                     NO_SPECULATION },
        VULNWL(CENTAUR, 5, X86_MODEL_ANY,                     NO_SPECULATION },
        VULNWL(INTEL,   5, X86_MODEL_ANY,                     NO_SPECULATION },
        VULNWL(NSC,     5, X86_MODEL_ANY,                     NO_SPECULATION },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_SALTWELL,          NO_SPECULATION },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_SALTWELL_TABLET,   NO_SPECULATION },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_SALTWELL_MID,      NO_SPECULATION },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_BONELL,            NO_SPECULATION },

        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_SILVERMONT,      NO_SSB | NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_SILVERMONT_,     NO_SSB | NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_SILVERMONT_MID,  NO_SSB | NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_AIRMONT,         NO_SSB | NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_AIRMONT_MID,     NO_SSB | NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_CORE_YONAH,           NO_SSB | NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_XEON_PHI_KNL,         NO_SSB | NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_XEON_PHI_KNM,         NO_SSB | NO_L1TF },

        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_GOLDMONT,                 NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_GOLDMONT_X,               NO_L1TF },
        VULNWL(INTEL,   6, INTEL_FAM6_ATOM_GOLDMONT_PLUS,            NO_L1TF },

        VULNWL(AMD,     0x0f, X86_MODEL_ANY,                NO_SSB           },
        VULNWL(AMD,     0x10, X86_MODEL_ANY,                NO_SSB           },
        VULNWL(AMD,     0x11, X86_MODEL_ANY,                NO_SSB           },
        VULNWL(AMD,     0x12, X86_MODEL_ANY,                NO_SSB           },

        /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
        VULNWL(AMD,     X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF },
        VULNWL(HYGON,   X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF },
        {}
};

Thanks,

	tglx