From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 01 Mar 2019 16:03:41 -0000 Received: from p5492e5b8.dip0.t-ipconnect.de ([84.146.229.184] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gzkdQ-00078G-1j for speck@linutronix.de; Fri, 01 Mar 2019 17:03:40 +0100 Date: Fri, 1 Mar 2019 17:03:39 +0100 (CET) From: Thomas Gleixner Subject: Re: [patch V5 09/14] MDS basics 9 In-Reply-To: <20190301140415.pjv7qjellvqrlbw5@treble> Message-ID: References: <20190227150939.605235753@linutronix.de> <20190227152037.818666801@linutronix.de> <20190301140415.pjv7qjellvqrlbw5@treble> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Fri, 1 Mar 2019, speck for Josh Poimboeuf wrote: > On Wed, Feb 27, 2019 at 04:09:48PM +0100, speck for Thomas Gleixner wrote: > > Subject: [patch V5 09/14] x86/speculation/mds: Conditionally clear CPU buffers on idle entry > > From: Thomas Gleixner > > > > Add a static key which controls the invocation of the CPU buffer clear > > mechanism on idle entry. This is independent of other MDS mitigations > > because the idle entry invocation to mitigate the potential leakage due to > > store buffer repartitioning is only necessary on SMT systems. > > > > Add the actual invocations to the different halt/mwait variants which > > covers all usage sites. mwaitx is not patched as it's not available on > > Intel CPUs. > > > > The buffer clear is only invoked before entering the C-State to prevent > > that stale data from the idling CPU is spilled to the Hyper-Thread sibling > > after the Store buffer got repartitioned and all entries are available to > > the non idle sibling. > > Andrea brought up a good question privately -- this patch mitigates > MSBDS for HT, but HT will still be susceptible to the other two MDS > issues. So what's the point? It seems this patch only protects people > who don't care about MDS in the first place. Indeed for most CPU models it's pointless. The ones which are only affected by MSBDS are Atom Silvermont/Airmont which are all single threaded and the XEON PHIs. For XEON PHI it actually makes sense because XEON PHI does not have L1TF either. But yes, for everything else it's just window dressing. Thanks, tglx