Re: [PATCH v6 1/5] NX 1

[Thomas Gleixner <tglx@linutronix.de>]

On Fri, 11 Oct 2019, speck for Paolo Bonzini wrote:

This one and all other patches lack a

  From: ...
  Subject: ...
  
in the mail body, which requires manual fiddling with those patches when
applying them.

> Some processors may incur a machine check error possibly
> resulting in an unrecoverable cpu hang when an instruction fetch
> encounters a TLB multi-hit in the instruction TLB. This can occur
> when the page size is changed along with either the physical
> address or cache type [1].
> 
> This issue affects both bare-metal x86 page tables and EPT.
> 
> This can be mitigated by either eliminating the use of large
> pages or by using careful TLB invalidations when changing the
> page size in the page tables.
> 
> Just like Spectre, Meltdown, L1TF and MDS, a new bit has been
> allocated in MSR_IA32_ARCH_CAPABILITIES (PSCHANGE_MC_NO) and will
> be set on CPUs which are mitigated against this issue.
> 
> [1] For example please refer to erratum SKL002 in "6th Generation
> Intel Processor Family Specification Update"
> https://www.intel.com/content/www/us/en/products/docs/processors/core/desktop-6th-gen-core-family-spec-update.html
> https://www.google.com/search?q=site:intel.com+SKL002

Please don't provide links like this. They first one will be outdated in
the worst case before this goes public. The second one is giving the right
answer today, but does it so in 5 years from now?

I asked a gazillion times in the past to stick a copy of the errata PDF
into bugzilla.kernel.org and provide a link to the BZ entry. That has a
decent chance to be a permalink.

Sure, we don't want a public bugzilla entry for this right now, but we can
create a dummy entry and update the subject plus upload the file when the
stuff goes public.

      https://bugzilla.kernel.org/show_bug.cgi?id=205195

is innocent enough for this.

Thanks,

	tglx