[MODERATED] ...

[Jon Masters <jcm@redhat.com>]

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Subject: Re: [PATCH v7 01/10] TAAv7 1

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On 10/22/19 1:26 PM, speck for Josh Poimboeuf wrote:
> On Mon, Oct 21, 2019 at 01:23:02PM -0700, speck for Pawan Gupta wrote:
>> From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
>> Subject: [PATCH v7 01/10] x86/tsx: Add enumeration support for IA32_TSX_CTRL
>>  MSR
>>
>> Transactional Synchronization Extensions (TSX) may be used on certain
>> processors as part of a speculative side channel attack.  A microcode
>> update for existing processors that are vulnerable to this attack will
>> add a new MSR, IA32_TSX_CTRL to allow the system administrator the
>> option to disable TSX as one of the possible mitigations.  [Note that
>> future processors that are not vulnerable will also support the
>> IA32_TSX_CTRL MSR].
> 
> This should clarify that not *all* TAA-vulnerable CPUs will get
> IA32_TSX_CTRL, instead only the ones which aren't vulnerable to MDS.

And FYI this is a change from what Intel had originally said. I think
we're all on the same page now that IA32_TSX_CTRL is only going to exist
on a small number of processors (those with MDS_NO=1 vulnerable to TAA).
We need a comprehensive list of designs in flight shared at some point
(privately) too, so that vendors can prepare documentation ahead.

I believe IA32_TSX_CTRL will be implemented going forward, even on next
generation processors without TAA. Please document that this control
interface is going to persist if that is indeed still the plan.

Jon.

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