From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 21 Oct 2019 23:01:16 -0000 Received: from esa6.hc3370-68.iphmx.com ([216.71.155.175]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMgfo-0003Y3-Jg for speck@linutronix.de; Tue, 22 Oct 2019 01:01:13 +0200 Subject: [MODERATED] Re: [PATCH v5 08/11] TAAv5 8 References: <20191015103454.GW317@dhcp22.suse.cz> <20191016075434.GL317@dhcp22.suse.cz> <20191016092333.GQ317@dhcp22.suse.cz> <20191018001407.GA28905@guptapadev.amr> <20191021125429.GP9379@dhcp22.suse.cz> <20191021200139.GA23497@guptapadev.amr> <20191021203338.uhkjj2ixa36ysdvm@treble> <20191021203440.73dl2q5lucu5eiaq@treble> <20191021203335.GC23497@guptapadev.amr> From: Andrew Cooper Message-ID: Date: Tue, 22 Oct 2019 00:01:01 +0100 MIME-Version: 1.0 In-Reply-To: <20191021203335.GC23497@guptapadev.amr> Content-Type: multipart/mixed; boundary="6hZbrHWjNnGIJn1nvT2tZNyi0FNQCdxt5"; protected-headers="v1" To: speck@linutronix.de List-ID: --6hZbrHWjNnGIJn1nvT2tZNyi0FNQCdxt5 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Language: en-GB On 21/10/2019 21:33, speck for Pawan Gupta wrote: > On Mon, Oct 21, 2019 at 03:34:40PM -0500, speck for Josh Poimboeuf wrot= e: >> On Mon, Oct 21, 2019 at 03:33:38PM -0500, Josh Poimboeuf wrote: >>> On Mon, Oct 21, 2019 at 01:01:39PM -0700, speck for Pawan Gupta wrote= : >>>> On Mon, Oct 21, 2019 at 02:54:29PM +0200, speck for Michal Hocko wro= te: >>>>> On Thu 17-10-19 17:14:07, speck for Pawan Gupta wrote: >>>>> [...] >>>>>> Let me know if there are any questions. >>>>> is there any list of CPUs that would benefit from tsx=3Dauto compar= ed to >>>>> tsx=3Don? In other words do we really need both? >>>> Below is the list of TAA affected CPUs that will get TSX_CTRL MSR. >>>> >>>> +----------------------------+------------------+------------+ >>>> | Name | Family / model | Stepping | >>>> +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ >>>> | Whiskey Lake (ULT refresh) | 06_8E | 0xC | >>>> +----------------------------+------------------+------------+ >>>> | 2nd gen Cascade Lake | 06_55 | 6, 7 | >>>> +----------------------------+------------------+------------+ >>>> | Coffee Lake R | 06_9E | 0xD | >>>> +----------------------------+------------------+------------+ >>>> >>>> tsx=3Dauto on these CPUs will disable TSX. >>>> tsx=3Don will keep TSX enabled. >> [ Please ignore my previous email, it had a glaring typo ] >> >> Just to clarify, is this list identical to the list of CPUs which are >> vulnerable to TAA and have MDS_NO=3D1? > That is correct. What about Commit Lake parts, because that is explicitly called out in the list of MDS_NO=3D1, TAA-vulnerable parts in initial whitepaper about = TAA. ~Andrew --6hZbrHWjNnGIJn1nvT2tZNyi0FNQCdxt5--