From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Cc: Tomas Winkler <tomas.winkler@intel.com>, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions)
Date: Fri, 2 Jul 2021 13:22:59 +0100 [thread overview]
Message-ID: <01bcc598-8ebd-cc3f-1aa4-9d4dcc6f51f1@linux.intel.com> (raw)
In-Reply-To: <20210701202427.1547543-8-matthew.d.roper@intel.com>
On 01/07/2021 21:23, Matt Roper wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Xe_HP can have a lot of extra media engines. This patch adds the basic
> definitions for them.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 ++-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 50 ++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 ++++--
> drivers/gpu/drm/i915/i915_reg.h | 6 +++
> 4 files changed, 69 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 87b06572fd2e..35edc55720f4 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -279,7 +279,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> if (mode & EMIT_INVALIDATE)
> aux_inv = rq->engine->mask & ~BIT(BCS0);
> if (aux_inv)
> - cmd += 2 * hweight8(aux_inv) + 2;
> + cmd += 2 * hweight32(aux_inv) + 2;
>
> cs = intel_ring_begin(rq, cmd);
> if (IS_ERR(cs))
> @@ -313,9 +313,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> struct intel_engine_cs *engine;
> unsigned int tmp;
>
> - *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
> - for_each_engine_masked(engine, rq->engine->gt,
> - aux_inv, tmp) {
> + *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
> + for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
> *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
> *cs++ = AUX_INV;
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 4ab2c9abb943..6e2aa1acc4d4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -104,6 +104,38 @@ static const struct engine_info intel_engines[] = {
> { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
> },
> },
> + [VCS4] = {
> + .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
> + .class = VIDEO_DECODE_CLASS,
> + .instance = 4,
> + .mmio_bases = {
> + { .graphics_ver = 11, .base = XEHP_BSD5_RING_BASE }
> + },
> + },
> + [VCS5] = {
> + .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
> + .class = VIDEO_DECODE_CLASS,
> + .instance = 5,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
> + },
> + },
> + [VCS6] = {
> + .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
> + .class = VIDEO_DECODE_CLASS,
> + .instance = 6,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
> + },
> + },
> + [VCS7] = {
> + .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
> + .class = VIDEO_DECODE_CLASS,
> + .instance = 7,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
> + },
> + },
> [VECS0] = {
> .hw_id = VECS0_HW,
> .class = VIDEO_ENHANCEMENT_CLASS,
> @@ -121,6 +153,22 @@ static const struct engine_info intel_engines[] = {
> { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
> },
> },
> + [VECS2] = {
> + .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
> + .class = VIDEO_ENHANCEMENT_CLASS,
> + .instance = 2,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
> + },
> + },
> + [VECS3] = {
> + .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
> + .class = VIDEO_ENHANCEMENT_CLASS,
> + .instance = 3,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
> + },
> + },
> };
>
> /**
> @@ -269,6 +317,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
>
> BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
> BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
> + BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
> + BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
>
> if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 5b91068ab277..b25f594a7e4b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -46,7 +46,7 @@
> #define COPY_ENGINE_CLASS 3
> #define OTHER_CLASS 4
> #define MAX_ENGINE_CLASS 4
> -#define MAX_ENGINE_INSTANCE 3
> +#define MAX_ENGINE_INSTANCE 7
>
> #define I915_MAX_SLICES 3
> #define I915_MAX_SUBSLICES 8
> @@ -64,7 +64,7 @@ struct intel_gt;
> struct intel_ring;
> struct intel_uncore;
>
> -typedef u8 intel_engine_mask_t;
> +typedef u32 intel_engine_mask_t;
u16 would be enough but it's probably pointless unless it makes it
better considering what I'll write next.
What I'd do is reorder the fields in struct intel_gt_info to avoid
padding, probably just pulling l3bank_mask up to be second is best.
Similar for struct intel_device_info because there's a ton of those and
so historically we were actually laying it out with care. A perfect
solution while keeping logical grouping might not be possible but worth
having a look.
Regards,
Tvrtko
> #define ALL_ENGINES ((intel_engine_mask_t)~0ul)
>
> struct intel_hw_status_page {
> @@ -101,8 +101,8 @@ struct i915_ctx_workarounds {
> struct i915_vma *vma;
> };
>
> -#define I915_MAX_VCS 4
> -#define I915_MAX_VECS 2
> +#define I915_MAX_VCS 8
> +#define I915_MAX_VECS 4
>
> /*
> * Engine IDs definitions.
> @@ -115,9 +115,15 @@ enum intel_engine_id {
> VCS1,
> VCS2,
> VCS3,
> + VCS4,
> + VCS5,
> + VCS6,
> + VCS7,
> #define _VCS(n) (VCS0 + (n))
> VECS0,
> VECS1,
> + VECS2,
> + VECS3,
> #define _VECS(n) (VECS0 + (n))
> I915_NUM_ENGINES
> #define INVALID_ENGINE ((enum intel_engine_id)-1)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f7dad8541417..d4546e871833 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2516,9 +2516,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN11_BSD2_RING_BASE 0x1c4000
> #define GEN11_BSD3_RING_BASE 0x1d0000
> #define GEN11_BSD4_RING_BASE 0x1d4000
> +#define XEHP_BSD5_RING_BASE 0x1e0000
> +#define XEHP_BSD6_RING_BASE 0x1e4000
> +#define XEHP_BSD7_RING_BASE 0x1f0000
> +#define XEHP_BSD8_RING_BASE 0x1f4000
> #define VEBOX_RING_BASE 0x1a000
> #define GEN11_VEBOX_RING_BASE 0x1c8000
> #define GEN11_VEBOX2_RING_BASE 0x1d8000
> +#define XEHP_VEBOX3_RING_BASE 0x1e8000
> +#define XEHP_VEBOX4_RING_BASE 0x1f8000
> #define BLT_RING_BASE 0x22000
> #define RING_TAIL(base) _MMIO((base) + 0x30)
> #define RING_HEAD(base) _MMIO((base) + 0x34)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-02 12:23 UTC|newest]
Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 20:23 [Intel-gfx] [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 01/53] drm/i915: Add "release id" version Matt Roper
2021-07-02 12:33 ` Tvrtko Ursulin
2021-07-05 11:52 ` Jani Nikula
2021-07-06 21:09 ` Lucas De Marchi
2021-07-07 8:34 ` Jani Nikula
2021-07-07 15:40 ` Lucas De Marchi
2021-07-06 20:57 ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 02/53] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 03/53] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-02 9:21 ` Daniel Vetter
2021-07-06 22:48 ` Lucas De Marchi
2021-07-07 7:39 ` Daniel Vetter
2021-07-07 15:53 ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-01 22:06 ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-01 22:19 ` Lucas De Marchi
2021-07-02 12:08 ` Tvrtko Ursulin
2021-07-01 20:23 ` [Intel-gfx] [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-01 22:33 ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-02 12:22 ` Tvrtko Ursulin [this message]
2021-07-07 22:17 ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-02 12:42 ` Tvrtko Ursulin
2021-07-06 21:15 ` Lucas De Marchi
2021-07-07 7:46 ` Tvrtko Ursulin
2021-07-01 20:23 ` [Intel-gfx] [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 11/53] drm/i915/xehp: Define multicast register ranges Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 12/53] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 13/53] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 14/53] drm/i915/xehp: handle new steering options Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-01 21:41 ` Rodrigo Vivi
2021-07-02 7:57 ` Jani Nikula
2021-07-07 22:20 ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 20/53] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-01 21:41 ` Rodrigo Vivi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 24/53] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 26/53] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 28/53] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-02 8:57 ` Lionel Landwerlin
2021-07-01 20:24 ` [Intel-gfx] [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 33/53] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-06 21:47 ` Lucas De Marchi
2021-07-01 20:24 ` [Intel-gfx] [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 37/53] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 38/53] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 40/53] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-02 8:14 ` Jani Nikula
2021-07-01 20:24 ` [Intel-gfx] [PATCH 45/53] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-02 8:16 ` Jani Nikula
2021-07-07 22:22 ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-09 18:25 ` Lucas De Marchi
2021-07-01 20:24 ` [Intel-gfx] [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Matt Roper
2021-07-02 8:19 ` Jani Nikula
2021-08-23 5:42 ` Kulkarni, Vandita
2021-07-01 20:24 ` [Intel-gfx] [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-09 0:11 ` Navare, Manasi
2021-07-01 20:24 ` [Intel-gfx] [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-02 1:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms Patchwork
2021-07-02 1:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-02 2:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-02 8:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-07 22:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev4) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=01bcc598-8ebd-cc3f-1aa4-9d4dcc6f51f1@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=matthew.d.roper@intel.com \
--cc=tomas.winkler@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).