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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 16/57] drm/i915: Extract request rewinding from execlists
Date: Tue, 2 Feb 2021 13:08:16 +0000
Message-ID: <054426ca-daaf-827d-f833-f402691bdad4@linux.intel.com> (raw)
In-Reply-To: <20210201085715.27435-16-chris@chris-wilson.co.uk>


On 01/02/2021 08:56, Chris Wilson wrote:
> In the process of preparing to reuse the request submission logic for
> other backends, lift it out of the execlists backend.
> 
> While this operates on the common structs, we do have a bit of backend
> knowledge, which is harmless for !lrc but still unsightly.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/intel_engine.h        |  3 -
>   .../drm/i915/gt/intel_execlists_submission.c  | 58 ++-----------------
>   drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  3 +
>   drivers/gpu/drm/i915/gt/selftest_execlists.c  |  2 +-
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  3 +-
>   drivers/gpu/drm/i915/i915_scheduler.c         | 44 ++++++++++++++
>   drivers/gpu/drm/i915/i915_scheduler.h         |  3 +
>   7 files changed, 56 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 8d9184920c51..cc2df80eb449 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -137,9 +137,6 @@ execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
>   	local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
>   }
>   
> -struct i915_request *
> -execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
> -
>   static inline u32
>   intel_read_status_page(const struct intel_engine_cs *engine, int reg)
>   {
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 51044387a8a2..b6dea80da533 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -359,56 +359,6 @@ assert_priority_queue(const struct i915_request *prev,
>   	return rq_prio(prev) >= rq_prio(next);
>   }
>   
> -static struct i915_request *
> -__unwind_incomplete_requests(struct intel_engine_cs *engine)
> -{
> -	struct i915_request *rq, *rn, *active = NULL;
> -	struct list_head *pl;
> -	int prio = I915_PRIORITY_INVALID;
> -
> -	lockdep_assert_held(&engine->active.lock);
> -
> -	list_for_each_entry_safe_reverse(rq, rn,
> -					 &engine->active.requests,
> -					 sched.link) {
> -		if (__i915_request_is_complete(rq)) {
> -			list_del_init(&rq->sched.link);
> -			continue;
> -		}
> -
> -		__i915_request_unsubmit(rq);
> -
> -		GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
> -		if (rq_prio(rq) != prio) {
> -			prio = rq_prio(rq);
> -			pl = i915_sched_lookup_priolist(engine, prio);
> -		}
> -		GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
> -
> -		list_move(&rq->sched.link, pl);
> -		set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> -
> -		/* Check in case we rollback so far we wrap [size/2] */
> -		if (intel_ring_direction(rq->ring,
> -					 rq->tail,
> -					 rq->ring->tail + 8) > 0)
> -			rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
> -
> -		active = rq;
> -	}
> -
> -	return active;
> -}
> -
> -struct i915_request *
> -execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
> -{
> -	struct intel_engine_cs *engine =
> -		container_of(execlists, typeof(*engine), execlists);
> -
> -	return __unwind_incomplete_requests(engine);
> -}
> -
>   static void
>   execlists_context_status_change(struct i915_request *rq, unsigned long status)
>   {
> @@ -1080,7 +1030,7 @@ static void defer_active(struct intel_engine_cs *engine)
>   {
>   	struct i915_request *rq;
>   
> -	rq = __unwind_incomplete_requests(engine);
> +	rq = __i915_sched_rewind_requests(engine);
>   	if (!rq)
>   		return;
>   
> @@ -1292,7 +1242,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>   			 * the preemption, some of the unwound requests may
>   			 * complete!
>   			 */
> -			__unwind_incomplete_requests(engine);
> +			__i915_sched_rewind_requests(engine);
>   
>   			last = NULL;
>   		} else if (timeslice_expired(engine, last)) {
> @@ -2287,7 +2237,7 @@ static void execlists_capture(struct intel_engine_cs *engine)
>   	 * which we return it to the queue for signaling.
>   	 *
>   	 * By removing them from the execlists queue, we also remove the
> -	 * requests from being processed by __unwind_incomplete_requests()
> +	 * requests from being processed by __intel_engine_rewind_requests()
>   	 * during the intel_engine_reset(), and so they will *not* be replayed
>   	 * afterwards.
>   	 *
> @@ -2878,7 +2828,7 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
>   	/* Push back any incomplete requests for replay after the reset. */
>   	rcu_read_lock();
>   	spin_lock_irqsave(&engine->active.lock, flags);
> -	__unwind_incomplete_requests(engine);
> +	__i915_sched_rewind_requests(engine);
>   	spin_unlock_irqrestore(&engine->active.lock, flags);
>   	rcu_read_unlock();
>   }
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> index 41e5350a7a05..364656bedec7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> @@ -92,4 +92,7 @@
>   /* in Gen12 ID 0x7FF is reserved to indicate idle */
>   #define GEN12_MAX_CONTEXT_HW_ID	(GEN11_MAX_CONTEXT_HW_ID - 1)
>   
> +#define CTX_DESC_RELOAD_PD BIT_ULL(1)
> +#define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
> +
>   #endif /* _INTEL_LRC_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> index 68e1398704a4..73340a96548f 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> @@ -4601,7 +4601,7 @@ static int reset_virtual_engine(struct intel_gt *gt,
>   
>   	/* Fake a preemption event; failed of course */
>   	spin_lock_irq(&engine->active.lock);
> -	__unwind_incomplete_requests(engine);
> +	__i915_sched_rewind_requests(engine);
>   	spin_unlock_irq(&engine->active.lock);
>   	GEM_BUG_ON(rq->engine != engine);
>   
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index dc33e5751776..aecede4f0943 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -306,14 +306,13 @@ static void guc_reset_state(struct intel_context *ce,
>   
>   static void guc_reset_rewind(struct intel_engine_cs *engine, bool stalled)
>   {
> -	struct intel_engine_execlists * const execlists = &engine->execlists;
>   	struct i915_request *rq;
>   	unsigned long flags;
>   
>   	spin_lock_irqsave(&engine->active.lock, flags);
>   
>   	/* Push back any incomplete requests for replay after the reset. */
> -	rq = execlists_unwind_incomplete_requests(execlists);
> +	rq = __i915_sched_rewind_requests(engine);
>   	if (!rq)
>   		goto out_unlock;
>   
> diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
> index 5e99f9779309..9fcfbf303ce0 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler.c
> +++ b/drivers/gpu/drm/i915/i915_scheduler.c
> @@ -6,6 +6,9 @@
>   
>   #include <linux/mutex.h>
>   
> +#include "gt/intel_ring.h"
> +#include "gt/intel_lrc_reg.h"
> +
>   #include "i915_drv.h"
>   #include "i915_globals.h"
>   #include "i915_request.h"
> @@ -542,6 +545,47 @@ void i915_request_enqueue(struct i915_request *rq)
>   		tasklet_hi_schedule(&engine->execlists.tasklet);
>   }
>   
> +struct i915_request *
> +__i915_sched_rewind_requests(struct intel_engine_cs *engine)
> +{
> +	struct i915_request *rq, *rn, *active = NULL;
> +	struct list_head *pl;
> +	int prio = I915_PRIORITY_INVALID;
> +
> +	lockdep_assert_held(&engine->active.lock);
> +
> +	list_for_each_entry_safe_reverse(rq, rn,
> +					 &engine->active.requests,
> +					 sched.link) {
> +		if (__i915_request_is_complete(rq)) {
> +			list_del_init(&rq->sched.link);
> +			continue;
> +		}
> +
> +		__i915_request_unsubmit(rq);
> +
> +		GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
> +		if (rq_prio(rq) != prio) {
> +			prio = rq_prio(rq);
> +			pl = i915_sched_lookup_priolist(engine, prio);
> +		}
> +		GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
> +
> +		list_move(&rq->sched.link, pl);
> +		set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> +
> +		/* Check in case we rollback so far we wrap [size/2] */
> +		if (intel_ring_direction(rq->ring,
> +					 rq->tail,
> +					 rq->ring->tail + 8) > 0)
> +			rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
> +
> +		active = rq;
> +	}
> +
> +	return active;
> +}
> +
>   void i915_sched_node_init(struct i915_sched_node *node)
>   {
>   	spin_lock_init(&node->lock);
> diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
> index 89d998f226e0..d3984f65b3a6 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler.h
> +++ b/drivers/gpu/drm/i915/i915_scheduler.h
> @@ -42,6 +42,9 @@ void i915_request_set_priority(struct i915_request *request, int prio);
>   
>   void i915_request_enqueue(struct i915_request *request);
>   
> +struct i915_request *
> +__i915_sched_rewind_requests(struct intel_engine_cs *engine);
> +
>   struct list_head *
>   i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio);
>   
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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  reply index

Thread overview: 103+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-01  8:56 [Intel-gfx] [PATCH 01/57] drm/i915/gt: Restrict the GT clock override to just Icelake Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 02/57] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
2021-02-01 14:34   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 03/57] drm/i915/selftests: Exercise cross-process context isolation Chris Wilson
2021-02-01 16:37   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 04/57] drm/i915: Protect against request freeing during cancellation on wedging Chris Wilson
2021-02-02  9:55   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 05/57] drm/i915: Take rcu_read_lock for querying fence's driver/timeline names Chris Wilson
2021-02-02 18:33   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 06/57] drm/i915/gt: Always flush the submission queue on checking for idle Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 07/57] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson
2021-02-02 11:57   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 08/57] drm/i915/gt: Move submission_method into intel_gt Chris Wilson
2021-02-02 12:03   ` Tvrtko Ursulin
2021-02-02 12:18     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 09/57] drm/i915: Replace engine->schedule() with a known request operation Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 10/57] drm/i915: Restructure priority inheritance Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 11/57] drm/i915/selftests: Measure set-priority duration Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 12/57] drm/i915/selftests: Exercise priority inheritance around an engine loop Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 13/57] drm/i915/selftests: Force a rewind if at first we don't succeed Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 14/57] drm/i915: Improve DFS for priority inheritance Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 15/57] drm/i915: Extract request submission from execlists Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 16/57] drm/i915: Extract request rewinding " Chris Wilson
2021-02-02 13:08   ` Tvrtko Ursulin [this message]
2021-02-01  8:56 ` [Intel-gfx] [PATCH 17/57] drm/i915: Extract request suspension from the execlists Chris Wilson
2021-02-02 13:15   ` Tvrtko Ursulin
2021-02-02 13:26     ` Chris Wilson
2021-02-02 13:32       ` Tvrtko Ursulin
2021-02-02 13:27     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 18/57] drm/i915: Extract the ability to defer and rerun a request later Chris Wilson
2021-02-02 13:18   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 19/57] drm/i915: Fix the iterative dfs for defering requests Chris Wilson
2021-02-02 14:10   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 20/57] drm/i915: Wrap access to intel_engine.active Chris Wilson
2021-02-04 11:07   ` Tvrtko Ursulin
2021-02-04 11:18     ` Chris Wilson
2021-02-04 11:56       ` Chris Wilson
2021-02-04 12:08         ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 21/57] drm/i915: Move common active lists from engine to i915_scheduler Chris Wilson
2021-02-04 11:12   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 22/57] drm/i915: Move scheduler queue Chris Wilson
2021-02-04 11:19   ` Tvrtko Ursulin
2021-02-04 11:32     ` Chris Wilson
2021-02-04 11:40     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 23/57] drm/i915: Move tasklet from execlists to sched Chris Wilson
2021-02-04 14:06   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 24/57] drm/i915/gt: Only kick the scheduler on timeslice/preemption change Chris Wilson
2021-02-04 14:09   ` Tvrtko Ursulin
2021-02-04 14:43     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 25/57] drm/i915: Move submit_request to i915_sched_engine Chris Wilson
2021-02-04 14:13   ` Tvrtko Ursulin
2021-02-04 14:45     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 26/57] drm/i915: Move finding the current active request to the scheduler Chris Wilson
2021-02-04 14:30   ` Tvrtko Ursulin
2021-02-04 14:59     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 27/57] drm/i915: Show execlists queues when dumping state Chris Wilson
2021-02-04 15:04   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 28/57] drm/i915: Wrap i915_request_use_semaphores() Chris Wilson
2021-02-04 15:05   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 29/57] drm/i915: Move scheduler flags Chris Wilson
2021-02-04 15:14   ` Tvrtko Ursulin
2021-02-04 16:05     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 30/57] drm/i915: Move timeslicing flag to scheduler Chris Wilson
2021-02-04 15:18   ` Tvrtko Ursulin
2021-02-04 16:11     ` Chris Wilson
2021-02-05  9:48       ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 31/57] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
2021-02-04 15:26   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 32/57] drm/i915: Move needs-breadcrumb flags to scheduler Chris Wilson
2021-02-04 15:28   ` Tvrtko Ursulin
2021-02-04 16:12     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 33/57] drm/i915: Move busywaiting control to the scheduler Chris Wilson
2021-02-04 15:32   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 34/57] drm/i915: Move preempt-reset flag " Chris Wilson
2021-02-04 15:34   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 35/57] drm/i915: Replace priolist rbtree with a skiplist Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 36/57] drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 37/57] drm/i915: Fair low-latency scheduling Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 38/57] drm/i915/gt: Specify a deadline for the heartbeat Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 39/57] drm/i915: Extend the priority boosting for the display with a deadline Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 40/57] drm/i915/gt: Support virtual engine queues Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 41/57] drm/i915: Move saturated workload detection back to the context Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 42/57] drm/i915: Bump default timeslicing quantum to 5ms Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 43/57] drm/i915/gt: Delay taking irqoff for execlists submission Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 44/57] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 45/57] drm/i915/gt: Track timeline GGTT offset separately from subpage offset Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 46/57] drm/i915/gt: Add timeline "mode" Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 47/57] drm/i915/gt: Use indices for writing into relative timelines Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 48/57] drm/i915/selftests: Exercise relative timeline modes Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 49/57] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 50/57] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 51/57] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 52/57] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 53/57] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 54/57] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 55/57] drm/i915/gt: Implement ring scheduler for gen4-7 Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 56/57] drm/i915/gt: Enable ring scheduling for gen5-7 Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 57/57] drm/i915: Support secure dispatch on gen6/gen7 Chris Wilson
2021-02-01 14:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/57] drm/i915/gt: Restrict the GT clock override to just Icelake Patchwork
2021-02-01 14:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-01 14:15 ` [Intel-gfx] [PATCH 01/57] " Mika Kuoppala
2021-02-01 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/57] " Patchwork
2021-02-01 19:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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Intel-GFX Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/intel-gfx/0 intel-gfx/git/0.git
	git clone --mirror https://lore.kernel.org/intel-gfx/1 intel-gfx/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 intel-gfx intel-gfx/ https://lore.kernel.org/intel-gfx \
		intel-gfx@lists.freedesktop.org
	public-inbox-index intel-gfx

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.freedesktop.lists.intel-gfx


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git