From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7A99C433E1 for ; Mon, 20 Jul 2020 10:35:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 82C4022482 for ; Mon, 20 Jul 2020 10:35:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 82C4022482 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 201A989A32; Mon, 20 Jul 2020 10:35:18 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9798C89A32 for ; Mon, 20 Jul 2020 10:35:16 +0000 (UTC) IronPort-SDR: WZqjj8FOH33IhStMyNVAW2lXHQKT1P6f5TtzsVX8qDAWKDkSiuJzwqEev1rU6Mn6IJ/7HeDkhW Pl7tSimO4pFA== X-IronPort-AV: E=McAfee;i="6000,8403,9687"; a="149040930" X-IronPort-AV: E=Sophos;i="5.75,374,1589266800"; d="scan'208";a="149040930" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2020 03:35:16 -0700 IronPort-SDR: I001Ld/rIggkcRVhl6fcNTcJeH/H7TR9/7XKI6NgOseH6XEeoWDyF9p6wER/fFuA2v3SI3LLKd MLrFZ+2mnO+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,374,1589266800"; d="scan'208";a="326026092" Received: from nirgilbo-mobl1.ger.corp.intel.com (HELO [10.251.168.123]) ([10.251.168.123]) by FMSMGA003.fm.intel.com with ESMTP; 20 Jul 2020 03:35:14 -0700 To: Chris Wilson , intel-gfx@lists.freedesktop.org References: <20200715115147.11866-1-chris@chris-wilson.co.uk> <20200715115147.11866-11-chris@chris-wilson.co.uk> From: Matthew Auld Message-ID: <10523b2b-fc58-3fd7-ac7f-ca8ec74434ae@intel.com> Date: Mon, 20 Jul 2020 11:35:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20200715115147.11866-11-chris@chris-wilson.co.uk> Content-Language: en-GB Subject: Re: [Intel-gfx] [PATCH 11/66] drm/i915: Preallocate stashes for vma page-directories X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 15/07/2020 12:50, Chris Wilson wrote: > We need to make the DMA allocations used for page directories to be > performed up front so that we can include those allocations in our > memory reservation pass. The downside is that we have to assume the > worst case, even before we know the final layout, and always allocate > enough page directories for this object, even when there will be overlap. > This unfortunately can be quite expensive, especially as we have to > clear/reset the page directories and DMA pages, but it should only be > required during early phases of a workload when new objects are being > discovered, or after memory/eviction pressure when we need to rebind. > Once we reach steady state, the objects should not be moved and we no > longer need to preallocating the pages tables. > > It should be noted that the lifetime for the page directories DMA is > more or less decoupled from individual fences as they will be shared > across objects across timelines. > > v2: Only allocate enough PD space for the PTE we may use, we do not need > to allocate PD that will be left as scratch. > v3: Store the shift unto the first PD level to encapsulate the different > PTE counts for gen6/gen8. > > Signed-off-by: Chris Wilson > Cc: Matthew Auld Fwiw, Reviewed-by: Matthew Auld _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx