From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: [PATCH 0/4] gtt cache coherency checker for i830 class hw Date: Sun, 9 May 2010 13:41:22 +0200 Message-ID: <1273405286-3560-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id AF03C9E801 for ; Sun, 9 May 2010 04:40:31 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org Hi all, This is part of my try-to-fix-i855-cache-coherency patch. It's essentially everything save the actual hacks to fix the gtt chipset flush (that simply not yet ready). The most important part is the cache coherency checker. I think merging this without any other fixes is worth it for a few reasons: - easier i8xx bug triaging: "random" crashes without any other applicable known issues but with some WARN_ONs due to failed chipset flushes suddenly get a decent explanation. - better assessment of how widespread this problem is: Given that my Thinkpad X40 happily spits out these traces when under use but is otherwise rather stable, we'll likely see a surge of bug reports. Perhaps even a top-ten spot on kerneloops.org :( ... - and one purely selfish reason: The patch I'm carrying around gets smaller ;) I've thought about whether to include a bz link in the dmesg output, but couldn't really decide one way or another. I fear that bz entry will get swamped under by totally useless me-too-and-all-intel-devs-suck reports. But on the other hand it's not really nice to waste testers time (creating nice bug reports) by not telling them that this is a know issue and where progress is tracked. Comments highly welcome. And when testing, don't get scared - at least on i855 getting the first failed flush before gdm finished drawing the login screen is kinda expected ;) Patches rebased against my two outstanding agp/gtt split-up patches, but should work on top of latest drm-intel-next, too. Yours, Daniel Daniel Vetter (4): agp/intel-gtt: steal the last gtt page drm/i915: add locking around chipset flush agp/intel-gtt: check cache-coherency on i830 class chipsets agp/intel-gtt: extract mch buffer flush in i830 chipset flush drivers/char/agp/intel-gtt.c | 163 +++++++++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_dma.c | 4 +- drivers/gpu/drm/i915/i915_gem.c | 3 + include/drm/intel-gtt.h | 8 ++ 4 files changed, 146 insertions(+), 32 deletions(-) create mode 100644 include/drm/intel-gtt.h