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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915: Relinquish any fence when changing cache levels
Date: Wed, 13 Apr 2011 19:01:11 +0100
Message-ID: <1302717671-1914-1-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <87bp0ahzwn.fsf@pollan.anholt.net>

This is vital to maintain our contract with the hw for not using fences
on snooped memory for older chipsets. It should have no impact
other than clearing the fence register (and updating the fence
bookkeeping) as any future IO access (page faults or pwrite/pread) will
be linear and go through the cached CPU domain.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c38b011..39c50eb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3358,6 +3358,16 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 		if (ret)
 			return ret;
 
+		/* Before SandyBridge, you could not use tiling or fence
+		 * registers with snooped memory, so relinquish any fences
+		 * currently pointing to our region in the aperture.
+		 */
+		if (INTEL_INFO(obj->base.dev)->gen < 6) {
+			ret = i915_gem_object_put_fence(obj);
+			if (ret)
+				return ret;
+		}
+
 		ret = i915_gem_gtt_bind_object(obj, cache_level);
 		if (ret)
 			return ret;
-- 
1.7.4.1

  parent reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-04-13 12:25 Chris Wilson
2011-04-13 16:36 ` Eric Anholt
2011-04-13 16:59   ` Chris Wilson
2011-04-13 18:01   ` Chris Wilson [this message]
2011-04-13 20:46     ` Daniel Vetter
2011-04-13 21:42       ` Chris Wilson

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