From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915: Redirect GTT mappings to the CPU page if cache-coherent
Date: Wed, 13 Apr 2011 19:35:52 +0100 [thread overview]
Message-ID: <1302719752-11605-1-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <87pqoqi1pu.fsf@pollan.anholt.net>
... or if we will need to perform a cache-flush on the object anyway.
Unless, of course, we need to use a fence register to perform tiling
operations during the transfer (in which case we are no longer on a
chipset for which we need to be extra careful not to write through the
GTT to a snooped page).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 41 ++++++++++++++++++++++++++++++++++++++-
1 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8b3007c..3c7443d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1211,12 +1211,43 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
trace_i915_gem_object_fault(obj, page_offset, true, write);
- /* Now bind it into the GTT if needed */
if (!obj->map_and_fenceable) {
ret = i915_gem_object_unbind(obj);
if (ret)
goto unlock;
}
+
+ /* If it is unbound or we are currently writing through the CPU
+ * domain, continue to do so. On older chipsets it is
+ * particularly important to avoid writing through the GTT to
+ * snooped pages or face dire consequences. At least that's what
+ * the docs say...
+ */
+ if (obj->tiling_mode == I915_TILING_NONE &&
+ (obj->cache_level != I915_CACHE_NONE ||
+ obj->base.write_domain == I915_GEM_DOMAIN_CPU)) {
+ struct page *page;
+
+ ret = i915_gem_object_set_to_cpu_domain(obj, write);
+ if (ret)
+ goto unlock;
+
+ obj->dirty = 1;
+ obj->fault_mappable = true;
+ mutex_unlock(&dev->struct_mutex);
+
+ page = read_cache_page_gfp(obj->base.filp->f_path.dentry->d_inode->i_mapping,
+ page_offset,
+ GFP_HIGHUSER | __GFP_RECLAIMABLE);
+ if (IS_ERR(page)) {
+ ret = PTR_ERR(page);
+ goto out;
+ }
+
+ vmf->page = page;
+ return VM_FAULT_LOCKED;
+ }
+
if (!obj->gtt_space) {
ret = i915_gem_object_bind_to_gtt(obj, 0, true);
if (ret)
@@ -1699,6 +1730,11 @@ i915_gem_object_truncate(struct drm_i915_gem_object *obj)
{
struct inode *inode;
+ /* We may have inserted the backing pages into our vma
+ * when fulfilling a pagefault whilst in the CPU domain.
+ */
+ i915_gem_release_mmap(obj);
+
/* Our goal here is to return as much of the memory as
* is possible back to the system as we are called from OOM.
* To do this we must instruct the shmfs to drop all of its
@@ -3691,6 +3727,9 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
if (obj->phys_obj)
i915_gem_detach_phys_object(dev, obj);
+ /* Discard all references to the backing storage for this object */
+ i915_gem_object_truncate(obj);
+
i915_gem_free_object_tail(obj);
}
--
1.7.4.1
next prev parent reply other threads:[~2011-04-13 18:36 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-12 20:31 i915 next Chris Wilson
2011-04-12 20:31 ` [PATCH 01/30] drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines Chris Wilson
2011-04-12 20:31 ` [PATCH 02/30] drm/i915: Move the vblank pre/post modeset to the common crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 03/30] drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 04/30] drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 05/30] drm/i915: Drop the remaining bit of Ironlake code from i9xx_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 06/30] drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 07/30] drm/i915: Drop remaining pre-Ironlake " Chris Wilson
2011-04-12 20:31 ` [PATCH 08/30] drm/i915: Clean up leftover DPLL and LVDS register choice from pch split Chris Wilson
2011-04-12 20:31 ` [PATCH 09/30] drm/i915: Fold the DPLL limit defines into the structs that use them Chris Wilson
2011-04-12 20:31 ` [PATCH 10/30] drm/i915: fix ilk rc6 teardown locking Chris Wilson
2011-04-12 20:31 ` [PATCH 11/30] drm/1915: ringbuffer wait for idle function Chris Wilson
2011-04-12 20:31 ` [PATCH 12/30] drm/i915: fix rc6 initialization on Ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 13/30] drm/i915: re-enable rc6 for ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 14/30] drm/i915: use i915_enable_rc6 on SNB too Chris Wilson
2011-04-12 20:31 ` [PATCH 15/30] drm/i915: Rename agp_type to cache_level Chris Wilson
2011-04-13 15:57 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 16/30] drm/i915: Mark the cursor and the overlay as being part of the display planes Chris Wilson
2011-04-13 16:00 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 17/30] drm/i915: Do not clflush snooped objects Chris Wilson
2011-04-13 16:04 ` Daniel Vetter
2011-04-13 17:34 ` Chris Wilson
2011-04-13 20:47 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 18/30] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-13 18:59 ` Daniel Vetter
2011-04-13 19:21 ` Chris Wilson
2011-04-13 22:27 ` [PATCH 1/3] drm/i915: Introduce i915_gem_object_finish_gpu() Chris Wilson
2011-04-13 22:27 ` [PATCH 2/3] drm/i915: Introduce i915_gem_object_finish_gtt() Chris Wilson
2011-04-13 22:27 ` [PATCH 3/3] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-12 20:31 ` [PATCH 19/30] drm/i915: Use the uncached domain for the display planes v2 Chris Wilson
2011-04-12 20:31 ` [PATCH 20/30] drm/i915: Use the CPU domain for snooped pwrites Chris Wilson
2011-04-12 20:31 ` [PATCH 21/30] drm/i915: Redirect GTT mappings to the CPU page if cache-coherent Chris Wilson
2011-04-13 15:57 ` Eric Anholt
2011-04-13 16:19 ` Chris Wilson
2011-04-13 18:35 ` Chris Wilson [this message]
2011-04-13 19:13 ` [PATCH] " Daniel Vetter
2011-04-13 19:47 ` Chris Wilson
2011-04-13 20:26 ` [PATCH] drm/i915: Prevent mmap access through the GTT of snooped pages Chris Wilson
2011-04-13 20:51 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 22/30] drm/i915: Use the LLC mode on gen6 for everything but display Chris Wilson
2011-04-13 19:15 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 23/30] drm/i915: Cache GT fifo count for SandyBridge Chris Wilson
2011-04-14 2:21 ` Ben Widawsky
2011-04-14 4:48 ` Ben Widawsky
2011-04-12 20:31 ` [PATCH 24/30] drm/i915: Refactor pwrite/pread to use single copy of get_user_pages Chris Wilson
2011-04-13 15:59 ` Eric Anholt
2011-04-13 17:24 ` Chris Wilson
2011-04-13 19:35 ` Eric Anholt
2011-04-13 19:26 ` Daniel Vetter
2011-04-13 19:56 ` Chris Wilson
2011-04-13 20:56 ` Daniel Vetter
2011-04-14 23:23 ` Ben Widawsky
2011-04-15 9:48 ` Paul Menzel
2011-04-16 8:03 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 25/30] drm/i915: s/addr & ~PAGE_MASK/offset_in_page(addr)/ Chris Wilson
2011-04-12 20:31 ` [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence Chris Wilson
2011-04-13 19:37 ` Daniel Vetter
2011-04-13 20:15 ` Chris Wilson
2011-04-13 20:58 ` Daniel Vetter
2011-04-13 21:37 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 27/30] drm/i915: Invalidate fenced read domains upon flush Chris Wilson
2011-04-13 19:43 ` Daniel Vetter
2011-04-13 20:38 ` Chris Wilson
2011-04-13 21:02 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 28/30] drm/i915: Pass the fence register number to be written Chris Wilson
2011-04-13 19:48 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 29/30] drm/i915: Track fence setup separately from fenced object lifetime Chris Wilson
2011-04-13 20:42 ` Daniel Vetter
2011-04-13 21:56 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 30/30] drm/i915: Only print out the actual number of fences for i915_error_state Chris Wilson
2011-04-13 7:26 ` i915 next Chris Wilson
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