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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 09/13] drm/i915: Use the uncached domain for the display planes
Date: Thu, 14 Apr 2011 10:03:43 +0100
Message-ID: <1302771827-26112-10-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <1302771827-26112-1-git-send-email-chris@chris-wilson.co.uk>

From: Eric Anholt <eric@anholt.net>

The simplest and common method for ensuring scanout coherency on all
chipsets is to mark the scanout buffers as uncached (and for
userspace to remember to flush the render cache every so often).

We can improve upon this for later generations by marking scanout
objects as GFDT and only flush those cachelines when required. However,
we start simple.

[v2: Move the set to uncached above the clflush.  Otherwise, we'd skip
the clflush and try to scan out data that was still sitting in the
cache.]

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c |   32 +++++++++++++++++++++++---------
 1 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3f1181b..ea8e7e2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3105,10 +3105,6 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
 	uint32_t old_read_domains;
 	int ret;
 
-	/* If the object is currently unbound, this is a no-op. */
-	if (obj->gtt_space)
-		return 0;
-
 	ret = i915_gem_object_flush_gpu_write_domain(obj);
 	if (ret)
 		return ret;
@@ -3120,14 +3116,32 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
 			return ret;
 	}
 
+	/* The display engine is not coherent with the LLC cache on gen6.  As
+	 * a result, we make sure that the pinning that is about to occur is
+	 * done with uncached PTEs. This is lowest common denominator for all
+	 * chipsets.
+	 *
+	 * However for gen6+, we could do better by using the GFDT bit instead
+	 * of uncaching, which would allow us to flush all the LLC-cached data
+	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
+	 */
+	ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
+	if (ret)
+		return ret;
+
 	i915_gem_object_flush_cpu_write_domain(obj);
 
-	old_read_domains = obj->base.read_domains;
-	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
+	/* If the object is not bound, it will be moved into the GTT domain
+	 * when pinned otherwise do so here.
+	 */
+	if (obj->gtt_space) {
+		old_read_domains = obj->base.read_domains;
+		obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
 
-	trace_i915_gem_object_change_domain(obj,
-					    old_read_domains,
-					    obj->base.write_domain);
+		trace_i915_gem_object_change_domain(obj,
+						    old_read_domains,
+						    obj->base.write_domain);
+	}
 
 	return 0;
 }
-- 
1.7.4.1

  parent reply index

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-04-14  9:03 i915 llc for -next Chris Wilson
2011-04-14  9:03 ` [PATCH 01/13] drm/i915: Rename agp_type to cache_level Chris Wilson
2011-04-14 12:39   ` Keith Packard
2011-04-14 20:57     ` [PATCH] " Chris Wilson
2011-04-14  9:03 ` [PATCH 02/13] drm/i915: Do not clflush snooped objects Chris Wilson
2011-04-14  9:03 ` [PATCH 03/13] drm/i915: Introduce i915_gem_object_finish_gpu() Chris Wilson
2011-04-14 16:01   ` Daniel Vetter
2011-04-14  9:03 ` [PATCH 04/13] drm/i915: Introduce i915_gem_object_finish_gtt() Chris Wilson
2011-04-14 16:12   ` Daniel Vetter
2011-04-14 20:20     ` Chris Wilson
2011-05-04 16:47   ` Keith Packard
2011-04-14  9:03 ` [PATCH 05/13] drm/i915/gtt: Split out i915_gem_gtt_rebind_object() Chris Wilson
2011-04-14 16:52   ` Daniel Vetter
2011-04-14  9:03 ` [PATCH 06/13] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-14 16:54   ` Daniel Vetter
2011-04-14  9:03 ` [PATCH 07/13] drm/i915: Mark the cursor and the overlay as being part of the display planes Chris Wilson
2011-05-04 17:09   ` Keith Packard
2011-05-04 18:28     ` Chris Wilson
2011-05-04 18:46       ` Keith Packard
2011-05-04 19:47         ` Chris Wilson
2011-04-14  9:03 ` [PATCH 08/13] drm/i915: Pin after setting to the display plane Chris Wilson
2011-04-14 17:34   ` Daniel Vetter
2011-04-14 21:31     ` Chris Wilson
2011-04-15  6:04   ` [PATCH 1/2] drm/i915: Combine pinning " Chris Wilson
2011-04-15  6:04     ` [PATCH 2/2] drm/i915: Use the uncached domain for the display planes Chris Wilson
2011-04-16 10:54       ` Daniel Vetter
2011-04-15 12:11     ` [PATCH 1/2] drm/i915: Combine pinning after setting to the display plane Daniel Vetter
2011-04-16  6:26       ` Chris Wilson
2011-04-16  6:27       ` [PATCH] drm/i915: Combine pinning with " Chris Wilson
2011-04-16 10:52         ` Daniel Vetter
2011-04-16 11:00           ` Chris Wilson
2011-04-14  9:03 ` Chris Wilson [this message]
2011-04-14  9:03 ` [PATCH 10/13] drm/i915: Use the CPU domain for snooped pwrites Chris Wilson
2011-04-14 17:40   ` Daniel Vetter
2011-04-14  9:03 ` [PATCH 11/13] drm/i915: Prevent mmap access through the GTT of snooped pages Chris Wilson
2011-05-04 17:30   ` Keith Packard
2011-04-14  9:03 ` [PATCH 12/13] drm/i915: Prevent mixing of snooped and tiling modes for old chipsets Chris Wilson
2011-04-14 17:43   ` Daniel Vetter
2011-04-14 20:26     ` Chris Wilson
2011-05-04 17:32   ` Keith Packard
2011-04-14  9:03 ` [PATCH 13/13] drm/i915: Use the LLC mode on gen6 for everything but display Chris Wilson
2011-04-15  6:12 ` i915 llc for -next Chris Wilson

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