From: Ben Widawsky <ben@bwidawsk.net>
To: intel-gfx@lists.freedesktop.org
Cc: mesa-dev@lists.freedesktop.org
Subject: [PATCH 04/11] i965: Move register spill offsets
Date: Fri, 24 Jun 2011 12:42:49 -0700 [thread overview]
Message-ID: <1308944576-12740-5-git-send-email-ben@bwidawsk.net> (raw)
In-Reply-To: <1308944576-12740-1-git-send-email-ben@bwidawsk.net>
Since the debug system routine will share scratch space with threads
doing register spilling, we must offset the registers to accomodate.
This is more easily accomplished (and less bug prone) in Mesa, so there
you go...
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 15 +++++++++++++--
src/mesa/drivers/dri/i965/brw_wm_emit.c | 2 ++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 6b7c434..ac48d8f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -452,6 +452,17 @@ fs_visitor::generate_discard(fs_inst *inst)
}
}
+static GLuint
+brw_get_scratch_offset(struct brw_context *brw, fs_inst *inst)
+{
+ /* Split buffer 50-50 */
+ if (brw->wm.debugging) {
+ return inst->offset + (brw->wm.scratch_bo->size / brw->wm_max_threads) / 2;
+ } else {
+ return inst->offset;
+ }
+}
+
void
fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src)
{
@@ -461,7 +472,7 @@ fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src)
retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
retype(src, BRW_REGISTER_TYPE_UD));
brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), 1,
- inst->offset);
+ brw_get_scratch_offset(brw, inst));
}
void
@@ -483,7 +494,7 @@ fs_visitor::generate_unspill(fs_inst *inst, struct brw_reg dst)
brw_MOV(p, brw_null_reg(), dst);
brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), 1,
- inst->offset);
+ brw_get_scratch_offset(brw, inst));
if (intel->gen == 4 && !intel->is_g4x) {
/* gen4 errata: destination from a send can't be used as a
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index f61757a..4ac94ee 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1560,6 +1560,8 @@ static void emit_spill( struct brw_wm_compile *c,
mov (1) r0.2<1>:d 0x00000080:d { Align1 NoMask }
send (16) null.0<1>:uw m1 r0.0<8;8,1>:uw 0x053003ff:ud { Align1 }
*/
+ if (p->brw->wm.debugging)
+ abort();
brw_oword_block_write_scratch(p, brw_message_reg(1), 2, slot);
}
--
1.7.5.2
next prev parent reply other threads:[~2011-06-24 19:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-24 19:42 [PATCH 0/11] Fragment shader debugging Ben Widawsky
2011-06-24 19:42 ` [PATCH 01/11] intel: shared header for " Ben Widawsky
2011-06-24 19:42 ` [PATCH 02/11] i965: step message register allocation Ben Widawsky
2011-06-25 0:29 ` Eric Anholt
2011-06-24 19:42 ` [PATCH 03/11] i965: copy in system routine, reserve extra scratch Ben Widawsky
2011-06-25 0:37 ` Eric Anholt
2011-06-26 0:16 ` Ben Widawsky
2011-06-24 19:42 ` Ben Widawsky [this message]
2011-06-24 19:42 ` [PATCH 05/11] i965: setup system routine Ben Widawsky
2011-06-25 0:39 ` Eric Anholt
2011-06-24 19:42 ` [PATCH 06/11] i965: emit breakpoints Ben Widawsky
2011-06-24 19:42 ` [PATCH 07/11] i965: attach to a listening debugger Ben Widawsky
2011-06-24 19:42 ` [PATCH 08/11] intel-gpu-tools: register range handling for forcewake hooks Ben Widawsky
2011-06-24 19:42 ` [PATCH 09/11] intel-gpu-tools/forcewaked: simple forcewake app Ben Widawsky
2011-06-24 19:42 ` [PATCH 10/11] debugging: add important debug regs Ben Widawsky
2011-06-24 19:42 ` [PATCH 11/11] debugging: shader debugging Ben Widawsky
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