From: Ben Widawsky <ben@bwidawsk.net>
To: intel-gfx@lists.freedesktop.org
Cc: mesa-dev@lists.freedesktop.org
Subject: [PATCH 05/11] i965: setup system routine
Date: Fri, 24 Jun 2011 12:42:50 -0700 [thread overview]
Message-ID: <1308944576-12740-6-git-send-email-ben@bwidawsk.net> (raw)
In-Reply-To: <1308944576-12740-1-git-send-email-ben@bwidawsk.net>
Upload the system routine as part of the invariant state if debugging.
Remove SIP setting if not debugging to make it more friendly for others
that may be debugging shaders or media kernels.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 24 +++++++++++-------------
1 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1f3b64f..2465bc0 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -633,19 +633,17 @@ static void upload_invarient_state( struct brw_context *brw )
}
}
}
-
- /* 0x61020000 State Instruction Pointer */
- {
- struct brw_system_instruction_pointer sip;
- memset(&sip, 0, sizeof(sip));
-
- sip.header.opcode = CMD_STATE_INSN_POINTER;
- sip.header.length = 0;
- sip.bits0.pad = 0;
- sip.bits0.system_instruction_pointer = 0;
- BRW_BATCH_STRUCT(brw, &sip);
- }
-
+ /* The system routine must be set after a change to Instruction base */
+ if (brw->wm.debugging) {
+ assert(brw->wm.system_routine != NULL);
+ /* assert instruction base == 0 */
+ BEGIN_BATCH(4);
+ OUT_BATCH(CMD_STATE_INSN_POINTER << 16);
+ OUT_RELOC(brw->wm.system_routine, I915_GEM_DOMAIN_RENDER, 0, 0);
+ OUT_BATCH(MI_FLUSH | 1 << 1);
+ OUT_BATCH(MI_NOOP);
+ ADVANCE_BATCH();
+ }
{
struct brw_vf_statistics vfs;
--
1.7.5.2
next prev parent reply other threads:[~2011-06-24 19:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-24 19:42 [PATCH 0/11] Fragment shader debugging Ben Widawsky
2011-06-24 19:42 ` [PATCH 01/11] intel: shared header for " Ben Widawsky
2011-06-24 19:42 ` [PATCH 02/11] i965: step message register allocation Ben Widawsky
2011-06-25 0:29 ` Eric Anholt
2011-06-24 19:42 ` [PATCH 03/11] i965: copy in system routine, reserve extra scratch Ben Widawsky
2011-06-25 0:37 ` Eric Anholt
2011-06-26 0:16 ` Ben Widawsky
2011-06-24 19:42 ` [PATCH 04/11] i965: Move register spill offsets Ben Widawsky
2011-06-24 19:42 ` Ben Widawsky [this message]
2011-06-25 0:39 ` [PATCH 05/11] i965: setup system routine Eric Anholt
2011-06-24 19:42 ` [PATCH 06/11] i965: emit breakpoints Ben Widawsky
2011-06-24 19:42 ` [PATCH 07/11] i965: attach to a listening debugger Ben Widawsky
2011-06-24 19:42 ` [PATCH 08/11] intel-gpu-tools: register range handling for forcewake hooks Ben Widawsky
2011-06-24 19:42 ` [PATCH 09/11] intel-gpu-tools/forcewaked: simple forcewake app Ben Widawsky
2011-06-24 19:42 ` [PATCH 10/11] debugging: add important debug regs Ben Widawsky
2011-06-24 19:42 ` [PATCH 11/11] debugging: shader debugging Ben Widawsky
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