From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adam Jackson Subject: [PATCH 1/7] drm: Fill in more of the DisplayPort DPCD registers Date: Tue, 12 Jul 2011 17:37:59 -0400 Message-ID: <1310506685-855-2-git-send-email-ajax@redhat.com> References: <1310506685-855-1-git-send-email-ajax@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F7ADA0252 for ; Tue, 12 Jul 2011 14:38:14 -0700 (PDT) Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p6CLcDaX017145 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 12 Jul 2011 17:38:14 -0400 Received: from ihatethathostname.lab.bos.redhat.com (ihatethathostname.lab.bos.redhat.com [10.16.43.238]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p6CLcDSC010130 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 12 Jul 2011 17:38:13 -0400 Received: from ihatethathostname.lab.bos.redhat.com (ihatethathostname.lab.bos.redhat.com [127.0.0.1]) by ihatethathostname.lab.bos.redhat.com (8.14.5/8.14.4) with ESMTP id p6CLcCpa000910 for ; Tue, 12 Jul 2011 17:38:12 -0400 Received: (from ajax@localhost) by ihatethathostname.lab.bos.redhat.com (8.14.5/8.14.5/Submit) id p6CLcCUO000909 for intel-gfx@lists.freedesktop.org; Tue, 12 Jul 2011 17:38:12 -0400 In-Reply-To: <1310506685-855-1-git-send-email-ajax@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Signed-off-by: Adam Jackson --- include/drm/drm_dp_helper.h | 95 +++++++++++++++++++++++++++++++++--------- 1 files changed, 74 insertions(+), 21 deletions(-) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 91567bb..940daa5 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -64,16 +64,38 @@ #define DP_DOWNSTREAMPORT_PRESENT 0x005 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 -/* 00b = DisplayPort */ -/* 01b = Analog */ -/* 10b = TMDS or HDMI */ -/* 11b = Other */ +# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) +# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) +# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) +# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) # define DP_FORMAT_CONVERSION (1 << 3) #define DP_MAIN_LINK_CHANNEL_CODING 0x006 +#define DP_DOWN_STREAM_PORT_COUNT 0x007 +# define DP_DWN_STREAM_PORT_COUNT_MASK 0x0f +# define DP_OUI_SUPPORT (1 << 7) + +#define DP_RECEIVE_PORT0_CAP_0 0x008 +#define DP_RECEIVE_PORT0_CAP_1 0x009 +#define DP_RECEIVE_PORT1_CAP_0 0x00a +#define DP_RECEIVE_PORT1_CAP_1 0x00b +/* receiver port capabilities */ +# define DP_RECEIVE_PORT_CAP0_LOCAL_EDID_PRESENT (1 << 1) +# define DP_RECEIVE_PORT_CAP0_ASSOCIATED_TO_PREVIOUS (1 << 2) +# define DP_RECEIVE_PORT_CAP1_BUFFER_SIZE(x) ((x + 1) * 32) + #define DP_TRAINING_AUX_RD_INTERVAL 0x00e +#define DP_DOWN_STREAM_PORT_CAP(x) (0x080 + (x & 0x7f)) +# define DP_DWN_STRM_PORT_TYPE_DP (0 << 0) +# define DP_DWN_STRM_PORT_TYPE_VGA (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_DVI (2 << 0) +# define DP_DWN_STRM_PORT_TYPE_HDMI (3 << 0) +# define DP_DWN_STRM_PORT_TYPE_NON_EDID (4 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x07 +# define DP_DWN_STRM_PORT_HPD (1 << 3) + /* link configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_BW_1_62 0x06 @@ -85,21 +107,18 @@ # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) #define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 +# define DP_TRAINING_PATTERN_DISABLE (0 << 0) +# define DP_TRAINING_PATTERN_1 (1 << 0) +# define DP_TRAINING_PATTERN_2 (2 << 0) +# define DP_TRAINING_PATTERN_3 (3 << 0) # define DP_TRAINING_PATTERN_MASK 0x3 - # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) - # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) @@ -109,7 +128,6 @@ #define DP_TRAINING_LANE1_SET 0x104 #define DP_TRAINING_LANE2_SET 0x105 #define DP_TRAINING_LANE3_SET 0x106 - # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) @@ -117,13 +135,11 @@ # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) @@ -133,6 +149,16 @@ #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 # define DP_SET_ANSI_8B10B (1 << 0) +#define DP_SINK_COUNT 0x200 +# define DP_SINK_COUNT_MASK 0x3f +# define DP_SINK_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +# define DP_IRQ_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) +# define DP_IRQ_AUTOMATED_TEST_REQUEST (1 << 1) +# define DP_IRQ_CP_IRQ (1 << 2) +# define DP_IRQ_SINK_SPECIFIC_IRQ (1 << 6) + #define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 # define DP_LANE_CR_DONE (1 << 0) @@ -144,15 +170,13 @@ DP_LANE_SYMBOL_LOCKED) #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) +# define DP_INTERLANE_ALIGN_DONE (1 << 0) +# define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +# define DP_LINK_STATUS_UPDATED (1 << 7) #define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) +# define DP_RECEIVE_PORT_0_STATUS (1 << 0) +# define DP_RECEIVE_PORT_1_STATUS (1 << 1) #define DP_ADJUST_REQUEST_LANE0_1 0x206 #define DP_ADJUST_REQUEST_LANE2_3 0x207 @@ -165,6 +189,35 @@ # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 +#define DP_TRAINING_SCORE_LANE0 0x208 +#define DP_TRAINING_SCORE_LANE1 0x209 +#define DP_TRAINING_SCORE_LANE2 0x20a +#define DP_TRAINING_SCORE_LANE3 0x20b + +/* register pairs for a 15-bit saturated error count */ +#define DP_SYMBOL_ERROR_COUNT_LANE0_LOW 0x210 +#define DP_SYMBOL_ERROR_COUNT_LANE0_HIGH 0x211 +#define DP_SYMBOL_ERROR_COUNT_LANE1_LOW 0x212 +#define DP_SYMBOL_ERROR_COUNT_LANE1_HIGH 0x213 +#define DP_SYMBOL_ERROR_COUNT_LANE2_LOW 0x214 +#define DP_SYMBOL_ERROR_COUNT_LANE2_HIGH 0x215 +#define DP_SYMBOL_ERROR_COUNT_LANE3_LOW 0x216 +#define DP_SYMBOL_ERROR_COUNT_LANE4_HIGH 0x217 +/* ... on the HIGH register */ +# define DP_SYMBOL_ERROR_COUNT_VALID (1 << 7) + +#define DP_SOURCE_IEEE_OUI_7_0 0x300 +#define DP_SOURCE_IEEE_OUI_15_8 0x301 +#define DP_SOURCE_IEEE_OUI_23_16 0x302 + +#define DP_SINK_IEEE_OUI_7_0 0x400 +#define DP_SINK_IEEE_OUI_15_8 0x401 +#define DP_SINK_IEEE_OUI_23_16 0x402 + +#define DP_BRANCH_IEEE_OUI_7_0 0x500 +#define DP_BRANCH_IEEE_OUI_15_8 0x501 +#define DP_BRANCH_IEEE_OUI_23_16 0x502 + #define DP_SET_POWER 0x600 # define DP_SET_POWER_D0 0x1 # define DP_SET_POWER_D3 0x2 -- 1.7.6