From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: [PATCH 03/10] i965: Reserve scratch space for debugger communication Date: Wed, 13 Jul 2011 13:51:45 -0700 Message-ID: <1310590312-21669-4-git-send-email-ben@bwidawsk.net> References: <1310590312-21669-1-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1310590312-21669-1-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: mesa-dev-bounces+gcvmd-mesa3d-493=gmane.org@lists.freedesktop.org Errors-To: mesa-dev-bounces+gcvmd-mesa3d-493=gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: mesa-dev@lists.freedesktop.org, Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org Since the debug system routine will share scratch space with threads doing register spilling, we must offset the registers to accommodate. This is more easily accomplished (and less bug prone) in Mesa. The debugger will only work with the new fragment shader backend. Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 15 +++++++++++++-- src/mesa/drivers/dri/i965/brw_wm_emit.c | 2 ++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index 1d89b8f..2cd613a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -455,6 +455,17 @@ fs_visitor::generate_discard(fs_inst *inst) } } +static GLuint +brw_get_scratch_offset(struct brw_context *brw, fs_inst *inst) +{ + /* Split buffer 50-50 */ + if (brw->wm.debugging) { + return inst->offset + (brw->wm.scratch_bo->size / brw->wm_max_threads) / 2; + } else { + return inst->offset; + } +} + void fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src) { @@ -464,7 +475,7 @@ fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src) retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD), retype(src, BRW_REGISTER_TYPE_UD)); brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), 1, - inst->offset); + brw_get_scratch_offset(brw, inst)); } void @@ -486,7 +497,7 @@ fs_visitor::generate_unspill(fs_inst *inst, struct brw_reg dst) brw_MOV(p, brw_null_reg(), dst); brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), 1, - inst->offset); + brw_get_scratch_offset(brw, inst)); if (intel->gen == 4 && !intel->is_g4x) { /* gen4 errata: destination from a send can't be used as a diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index f61757a..4ac94ee 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1560,6 +1560,8 @@ static void emit_spill( struct brw_wm_compile *c, mov (1) r0.2<1>:d 0x00000080:d { Align1 NoMask } send (16) null.0<1>:uw m1 r0.0<8;8,1>:uw 0x053003ff:ud { Align1 } */ + if (p->brw->wm.debugging) + abort(); brw_oword_block_write_scratch(p, brw_message_reg(1), 2, slot); } -- 1.7.6