From: Kenneth Graunke <kenneth@whitecape.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 09/10] render: Update pixel shader state for Ivybridge.
Date: Thu, 14 Jul 2011 14:21:22 -0700 [thread overview]
Message-ID: <1310678483-7494-10-git-send-email-kenneth@whitecape.org> (raw)
In-Reply-To: <1310678483-7494-1-git-send-email-kenneth@whitecape.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
src/i965_render.c | 38 +++++++++++++++++++++++++++++++++++---
1 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/src/i965_render.c b/src/i965_render.c
index 5222d1c..596d070 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -2657,6 +2657,37 @@ gen6_composite_wm_state(intel_screen_private *intel,
}
static void
+gen7_composite_wm_state(intel_screen_private *intel,
+ Bool has_mask,
+ drm_intel_bo *bo)
+{
+ int num_surfaces = has_mask ? 3 : 2;
+
+ if (intel->gen6_render_state.kernel == bo)
+ return;
+
+ intel->gen6_render_state.kernel = bo;
+
+ OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
+ OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
+ GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2));
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
+ (num_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+ OUT_BATCH(0); /* scratch space base offset */
+ OUT_BATCH(((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
+ GEN7_PS_ATTRIBUTE_ENABLE |
+ GEN7_PS_16_DISPATCH_ENABLE);
+ OUT_BATCH((6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
+ OUT_BATCH(0); /* kernel 1 pointer */
+ OUT_BATCH(0); /* kernel 2 pointer */
+}
+
+
+static void
gen6_composite_drawing_rectangle(intel_screen_private *intel,
PixmapPtr dest)
{
@@ -2809,12 +2840,13 @@ gen6_emit_composite_state(struct intel_screen_private *intel)
(src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE);
gen6_composite_sampler_state_pointers(intel, ps_sampler_state_bo);
gen6_composite_sf_state(intel, has_mask);
- gen6_composite_wm_state(intel,
- has_mask,
- render->wm_kernel_bo[composite_op->wm_kernel]);
if (ivb) {
+ gen7_composite_wm_state(intel, has_mask,
+ render->wm_kernel_bo[composite_op->wm_kernel]);
gen7_upload_binding_table(intel, intel->surface_table);
} else {
+ gen6_composite_wm_state(intel, has_mask,
+ render->wm_kernel_bo[composite_op->wm_kernel]);
gen6_upload_binding_table(intel, intel->surface_table);
}
gen6_composite_drawing_rectangle(intel, intel->render_dest);
--
1.7.4.4
next prev parent reply other threads:[~2011-07-14 21:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-14 21:21 [PATCH 00/10] UXA Render acceleration for Ivybridge Kenneth Graunke
2011-07-14 21:21 ` [PATCH 01/10] render: New Ivybridge assembly programs for render acceleration Kenneth Graunke
2011-07-14 21:21 ` [PATCH 02/10] render: Update SURFACE_STATE for Ivybridge Kenneth Graunke
2011-07-14 21:21 ` [PATCH 03/10] render: Update SAMPLER_STATE " Kenneth Graunke
2011-07-14 21:21 ` [PATCH 04/10] render: Set Address Modify Enable in 3DSTATE_VERTEX_BUFFERS on Gen7 Kenneth Graunke
2011-07-14 21:21 ` [PATCH 05/10] render: Update 3DPRIMITIVE for Ivybridge Kenneth Graunke
2011-07-14 21:21 ` [PATCH 06/10] Xv: Refactor out pipeline setup functions for future reuse in render Kenneth Graunke
2011-07-14 21:21 ` [PATCH 07/10] render: Refactor to use newly shared pipeline setup code in i965_3d.c Kenneth Graunke
2011-07-14 21:21 ` [PATCH 08/10] render: Use Ivybridge variants for 3D pipeline setup Kenneth Graunke
2011-07-14 21:21 ` Kenneth Graunke [this message]
2011-07-14 21:21 ` [PATCH 10/10] render: Enable RENDER acceleration on Ivybridge Kenneth Graunke
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