From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/2] drm/i915: adjust framebuffer base address on gen4+ Date: Thu, 05 Jul 2012 11:37:11 +0100 Message-ID: <1341484695_176981@CP5-2952> References: <1341483450-6385-1-git-send-email-daniel.vetter@ffwll.ch> <1341483450-6385-2-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 3320BA0E06 for ; Thu, 5 Jul 2012 03:38:19 -0700 (PDT) In-Reply-To: <1341483450-6385-2-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Thu, 5 Jul 2012 12:17:30 +0200, Daniel Vetter wrote: > The tileoffset register only supports a limited offset in x/y of 4096, > so for giant screen configuration with a shared fb we wrap around. > > Fix this by computing a linear offset in tiles (pages) and only use > the tileoffset register to offset within the tile. One thing I did spot after hitting send, is that we don't enforce that the new_fb has the same pitch as the old_fb when flipping. Whilst there are patching floating around to do so in the midlayer, we need to express that constraint now for this patch to be valid. -Chris -- Chris Wilson, Intel Open Source Technology Centre