From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915: Export ability of changing cache levels to userspace
Date: Tue, 10 Jul 2012 10:00:58 +0100 [thread overview]
Message-ID: <1341910859_237091@CP5-2952> (raw)
In-Reply-To: <20120710085402.GA5108@phenom.ffwll.local>
On Tue, 10 Jul 2012 10:54:02 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Jul 09, 2012 at 12:34:39PM +0100, Chris Wilson wrote:
> > enum i915_cache_level {
> > - I915_CACHE_NONE,
> > - I915_CACHE_LLC,
> > - I915_CACHE_LLC_MLC, /* gen6+ */
> > + I915_CACHE_NONE = I915_CACHE_LEVEL_NONE,
> > + I915_CACHE_LLC = I915_CACHE_LEVEL_LLC,
> > + I915_CACHE_LLC_MLC = I915_CACHE_LEVEL_LLC_MLC, /* gen6+ */
>
> LLC_MLC is a lie, it doesn't exist on gen6. And gen7 has something else
> called l3$ cache, but that seems to be more special-purpose in nature
> (hence I have a feeling it's better if userspace just sets the desired
> caching in the surface state).
>
> The other thing that's irking me is whether we want different names for
> different kinds of caching or not, i.e. whether we should split out
> pre-gen6 coherent mem from gen6+ coherent stuff. Also, on vlv we don't
> have a llc cache, but we can still support coherent memory like on gen6+
> with llc (it's just a bit slower for gpu-only use, hence not the default).
"Just a bit" will be an understatement judging by the snoopable
architectures upon which it is based. :-p
> I guess I'd bikeshed less if we color this I915_CACHE_LEVEL_CPU_COHERENT
> (and maybe add more specific variants in the future if we need them).
I was half thinking towards extensibility, but we are more likely to
need new ioctls rather than just add to this set of "cache levels".
I am happy with just having two levels in the userspace for this:
uncached, snoopable. They are generic enough to cover the last 7
generations, good enough for the next 3?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-07-10 9:01 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-09 11:34 [RFC] Set cache level ioctl Chris Wilson
2012-07-09 11:34 ` [PATCH 1/3] drm: Add colouring to the range allocator Chris Wilson
2012-07-10 9:21 ` Daniel Vetter
2012-07-10 9:29 ` Chris Wilson
2012-07-10 9:40 ` Daniel Vetter
2012-07-10 10:15 ` [PATCH 1/2] " Chris Wilson
2012-07-10 10:15 ` [PATCH 2/2] drm/i915: Segregate memory domains in the GTT using coloring Chris Wilson
2012-07-12 12:19 ` Daniel Vetter
2012-07-12 12:15 ` [PATCH 1/2] drm: Add colouring to the range allocator Daniel Vetter
2012-07-09 11:34 ` [PATCH 2/3] drm/i915: Segregate memory domains in the GTT using coloring Chris Wilson
2012-07-09 11:34 ` [PATCH 3/3] drm/i915: Export ability of changing cache levels to userspace Chris Wilson
2012-07-10 8:54 ` Daniel Vetter
2012-07-10 9:00 ` Chris Wilson [this message]
2012-07-10 9:27 ` [PATCH] " Chris Wilson
2012-07-18 18:06 ` Daniel Vetter
2012-07-26 10:34 ` Daniel Vetter
2012-07-26 10:49 ` [PATCH] drm/i915: Segregate memory domains in the GTT using coloring Chris Wilson
2012-07-26 11:00 ` Daniel Vetter
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