From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 3/6] drm/i915: Remove the per-ring write list Date: Fri, 13 Jul 2012 09:53:33 +0100 Message-ID: <1342169622_3451@CP5-2952> References: <1342106019-17806-1-git-send-email-chris@chris-wilson.co.uk> <1342106019-17806-4-git-send-email-chris@chris-wilson.co.uk> <20120712193716.GN5039@phenom.ffwll.local> <1342123681_2236@CP5-2952> <20120713083426.GA5721@phenom.ffwll.local> <1342169397_3437@CP5-2952> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 795729E7E7 for ; Fri, 13 Jul 2012 01:53:47 -0700 (PDT) In-Reply-To: <1342169397_3437@CP5-2952> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 13 Jul 2012 09:49:48 +0100, Chris Wilson wrote: > No. Because by the time the previous breadcrumb has been seen we are > guarranteed to have flushed the gpu caches. So any wait in the future we > have flushed the caches before returning. Egg on face time. The issue is on the waiter side, since we don't wait unless pending_gpu_write is set. Tracking the last write seqno seems safest when removing the gpu_write_list. -Chris -- Chris Wilson, Intel Open Source Technology Centre