From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] [CFT] drm/i915: Only set the down rps limit when at the loweset frequency Date: Wed, 25 Jul 2012 23:09:42 +0100 Message-ID: <1343254184_355@CP5-2952> References: <1343244729-12867-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id A84E5A0DEA for ; Wed, 25 Jul 2012 15:09:49 -0700 (PDT) In-Reply-To: <1343244729-12867-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 25 Jul 2012 21:32:09 +0200, Daniel Vetter wrote: > The power docs say that when the gt leaves rc6, it is in the lowest > frequency and only about 25 usec later will switch to the frequency > selected in GEN6_RPNSWREQ. If the downclock limit expires in that > window and the down limit is set to the lowest possible frequency, the > hw will not send the down interrupt. Which leads to a too high gpu > clock and wasted power. > > Chris Wilson already worked on this with > > commit 7b9e0ae6da0a7eaf2680a1a788f08df123724f3b > Author: Chris Wilson > Date: Sat Apr 28 08:56:39 2012 +0100 > > drm/i915: Always update RPS interrupts thresholds along with > frequency > > but got the logic inverted: The current code set the down limit as > long as we haven't reached it. Instead of only once with reached the > lowest frequency. Yup, that's different to the opposite of what I thought I was writing to comply with the guide. :( Note you also have to fix up intel_sanitize_pm(). -Chris -- Chris Wilson, Intel Open Source Technology Centre