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From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [PATCH 2/5] drm/i915: implement WaDisableRenderCachePipelinedFlush
Date: Thu, 18 Oct 2012 11:49:51 +0200
Message-ID: <1350553794-5534-3-git-send-email-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <1350553794-5534-1-git-send-email-daniel.vetter@ffwll.ch>

Comment says for eaglelake/cantiga, but it's listed in the ilk table,
too. So apply it to both.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a4162dd..1970c54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -661,6 +661,7 @@
 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
 
 #define CACHE_MODE_0	0x02120 /* 915+ only */
+#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
 #define   CM0_ZR_OPT_DISABLE      (1<<5)
 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 72f41aa..aa77639 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3397,6 +3397,10 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(_3D_CHICKEN2,
 		   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
 		   _3D_CHICKEN2_WM_READ_PIPELINED);
+
+	/* WaDisableRenderCachePipelinedFlush */
+	I915_WRITE(CACHE_MODE_0,
+		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
 }
 
 static void gen6_init_clock_gating(struct drm_device *dev)
@@ -3728,6 +3732,10 @@ static void g4x_init_clock_gating(struct drm_device *dev)
 	if (IS_GM45(dev))
 		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
+
+	/* WaDisableRenderCachePipelinedFlush */
+	I915_WRITE(CACHE_MODE_0,
+		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
 }
 
 static void crestline_init_clock_gating(struct drm_device *dev)
-- 
1.7.10.4

  parent reply index

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-18  9:49 [PATCH 0/5] pile of ilk related workarounds Daniel Vetter
2012-10-18  9:49 ` [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6 Daniel Vetter
2012-10-18 11:10   ` Chris Wilson
2012-10-18 12:14     ` [PATCH] drm/i915: implement WaIssueDummyWriteToWakeupFromRC6 Daniel Vetter
2012-10-18 12:16     ` Daniel Vetter
2012-10-18 11:17   ` [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6 Chris Wilson
2012-10-18 11:21     ` Daniel Vetter
2012-10-18 11:25   ` Lespiau, Damien
2012-10-18  9:49 ` Daniel Vetter [this message]
2012-10-18 11:21   ` [PATCH 2/5] drm/i915: implement WaDisableRenderCachePipelinedFlush Chris Wilson
2012-10-29 21:33     ` Daniel Vetter
2012-10-18  9:49 ` [PATCH 3/5] drm/i915: WaInsertNoopAfterBatchEndCommand Daniel Vetter
2012-10-18 11:24   ` Chris Wilson
2012-10-18 12:19     ` [PATCH] " Daniel Vetter
2012-10-18  9:49 ` [PATCH 4/5] drm/i915: implement WaDisableSpriteDestColorKey Daniel Vetter
2012-10-18 11:32   ` Chris Wilson
2012-10-18  9:49 ` [PATCH 5/5] drm/i915: document a few more already implemented ilk w/as Daniel Vetter

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