From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH] drm/i915: reset GPU after clock gating init Date: Thu, 15 Nov 2012 10:24:03 -0800 Message-ID: <1353003843-22947-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy12-pub.bluehost.com (50-87-16-10.unifiedlayer.com [50.87.16.10]) by gabe.freedesktop.org (Postfix) with SMTP id 3EF179E96F for ; Thu, 15 Nov 2012 10:23:27 -0800 (PST) Received: from [67.161.37.189] (port=55642 helo=jbarnes-desktop.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.76) (envelope-from ) id 1TZ462-0003KO-Db for intel-gfx@lists.freedesktop.org; Thu, 15 Nov 2012 11:23:26 -0700 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is needed for SNB at least after disabling CSunit clock gating, and shouldn't hurt on other platforms either. This fixes an issue on James's machine where RC6 wouldn't always get enabled. Tested-by: James Kukunas Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6d8a5ed..2fccd8f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8718,6 +8718,7 @@ void intel_modeset_init_hw(struct drm_device *dev) intel_prepare_ddi(dev); intel_init_clock_gating(dev); + intel_gpu_reset(dev); mutex_lock(&dev->struct_mutex); intel_enable_gt_powersave(dev); -- 1.7.9.5