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From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [PATCH] drm/i915: enable sdvo interrupt on pch platforms
Date: Sun,  9 Dec 2012 22:28:03 +0100
Message-ID: <1355088483-14326-1-git-send-email-daniel.vetter@ffwll.ch> (raw)

Noticed while strolling through docs. Might make a few dual-link dvi
users happy(ier).

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c |  4 +++-
 drivers/gpu/drm/i915/intel_sdvo.c    | 10 +++++++++-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2a5ea6..a981ff5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1673,7 +1673,7 @@
 #define   SDVO_ENABLE		(1 << 31)
 #define   SDVO_PIPE_B_SELECT	(1 << 30)
 #define   SDVO_STALL_SELECT	(1 << 29)
-#define   SDVO_INTERRUPT_ENABLE	(1 << 26)
+#define   SDVO_INTERRUPT_ENABLE_PCH	(1 << 23)
 /**
  * 915G/GM SDVO pixel multiplier.
  *
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e4e6c53..3256a34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2384,6 +2384,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 	assert_pipe_enabled(dev_priv, pipe);
 	assert_plane_enabled(dev_priv, plane);
 
+	/* Ironlake workaround, control phase pointer manually */
+	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
+
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
 	reg = FDI_RX_IMR(pipe);
@@ -2413,7 +2416,6 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 	udelay(150);
 
 	/* Ironlake workaround, enable clock pointer after FDI enable*/
-	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
 	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
 		   FDI_RX_PHASE_SYNC_POINTER_EN);
 
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index c275bf0..a9b34f0 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1085,6 +1085,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
 	if (!mode)
 		return;
 
+	/* Preserve the PCH interrupt enable bit. */
+	sdvox = I915_READ(intel_sdvo->sdvo_reg) & SDVO_INTERRUPT_ENABLE_PCH;
+
 	/* First, set the input mapping for the first input to our controlled
 	 * output. This is only correct if we're a single-input device, in
 	 * which case the first input is the output from the appropriate SDVO
@@ -2775,9 +2778,14 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
 	/* Only enable the hotplug irq if we need it, to work around noisy
 	 * hotplug lines.
 	 */
-	if (intel_sdvo->hotplug_active)
+	if (intel_sdvo->hotplug_active) {
 		dev_priv->hotplug_supported_mask |= hotplug_mask;
 
+		if (HAS_PCH_SPLIT(dev))
+			intel_sdvo_write_sdvox(intel_sdvo,
+					       SDVO_INTERRUPT_ENABLE_PCH);
+	}
+
 	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
 
 	/* Set the input timing to the screen. Assume always input 0. */
-- 
1.7.11.7

             reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-12-09 21:28 Daniel Vetter [this message]
2012-12-09 21:30 ` Daniel Vetter
2012-12-09 21:35 ` Daniel Vetter
2012-12-10  0:37 ` Daniel Vetter
2012-12-10 21:20   ` Jesse Barnes
2012-12-10 21:29     ` Daniel Vetter

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