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From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw
Date: Wed, 30 Jan 2013 15:59:56 +0100
Message-ID: <1359557997-20308-1-git-send-email-daniel.vetter@ffwll.ch> (raw)

Dumps annoying noise into the dmesg:

[drm:intel_set_power_well] *ERROR* Timeout enabling power well

Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_pm.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 64d65f5..703219c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4053,6 +4053,9 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
 	bool is_enabled, enable_requested;
 	uint32_t tmp;
 
+	if (!IS_HASWELL(dev))
+		return;
+
 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 	is_enabled = tmp & HSW_PWR_WELL_STATE;
 	enable_requested = tmp & HSW_PWR_WELL_ENABLE;
-- 
1.7.10.4

             reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-30 14:59 Daniel Vetter [this message]
2013-01-30 14:59 ` [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code Daniel Vetter
2013-01-30 17:40   ` Rodrigo Vivi
2013-01-30 15:55 ` [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Sedat Dilek
2013-01-30 18:57 ` Paulo Zanoni
2013-01-30 19:04   ` Daniel Vetter

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